Low-power CMOS front-ends for wireless personal area networks

The potential of implementing subthreshold radio frequency circuits in deep sub-micron CMOS technology was investigated for developing low-power front-ends for wireless personal area network (WPAN) applications. It was found that the higher transconductance to bias current ratio in weak inversion could be exploited in developing low-power wireless front-ends, if circuit techniques are employed to mitigate the higher device noise in subthreshold region. The first fully integrated subthreshold low noise amplifier was demonstrated in the GHz frequency range requiring only 260 μW of power consumption. Novel subthreshold variable gain stages and down-conversion mixers were developed. A 2.4 GHz receiver, consuming 540 μW of power, was implemented using a new subthreshold mixer by replacing the conventional active low noise amplifier by a series-resonant passive network that provides both input matching and voltage amplification. The first fully monolithic subthreshold CMOS receiver was also implemented with integrated subthreshold quadrature LO (Local Oscillator) chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage amplification, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling were combined to lower the total power consumption to 2.6 mW. Extremely compact resistive feedback CMOS low noise amplifiers were presented as a cost-effective alternative to narrow band LNAs using high-Q inductors. Techniques to improve linearity and reduce power consumption were presented. The combination of high linearity, low noise figure, high broadband gain, extremely small die area and low power consumption made the proposed LNA architecture a compelling choice for many wireless applications.Ph.D.Committee Chair: Laskar, Joy; Committee Member: Chakraborty, Sudipto; Committee Member: Chang, Jae Joon; Committee Member: Divan, Deepakraj; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanoui

A Fully integrated D-band Direct-Conversion I/Q Transmitter and Receiver Chipset in SiGe BiCMOS Technology

This paper presents design and characterization of single-chip 110-170 GHz (D-band) direct conversion in-phase/quadrature-phase (I/Q) transmitter and receiver monolithic microwave integrated circuits (MMICs), realized in a 130 nm SiGe BiCMOS process with ft/fmax of 250 GHz/370 GHz. The chipset is suitable for low power wideband communication and can be used in both homodyne and heterodyne architectures. The Transmitter chip consists of a six-stage power amplifier, an I/Q modulator, and a LO multiplier chain. The LO multiplier chain consists of frequency sixtupler followed by a two-stage amplifier. It exhibits a single sideband conversion gain of 23 dB and saturated output power of 0 dBm. The 3 dB RF bandwidth is 31 GHz from 114 to 145 GHz. The receiver includes a low noise amplifier, I/Q demodulator and x6 multiplier chain at the LO port. The receiver provides a conversion gain of 27 dB and has a noise figure of 10 dB. It has 3 dB RF bandwidth of 28 GHz from 112-140 GHz. The transmitter and receiver have dc power consumption of 240 mW and 280 mW, respectively. The chip area of each transmitter and receiver circuit is 1.4 mm x 1.1 mm

Développement d'une architecture innovante de récepteur radar à 77 GHz et démonstration en CMOS 28 nm FDSOI

Grâce à sa capacité à détecter des cibles éloignées malgré une mauvaise visibilité, le radar automobile à 77 GHz joue un rôle important dans l'aide à la conduite. L'utilisation des fréquences millimétriques offre une bonne résolution et une importante capacité d'intégration des circuits. C'est aussi un défi car il faut satisfaire un cahier des charges exigeant sur le bruit et la linéarité du récepteur. Les technologies SiGe BiCMOS ont été les premières utilisées pour la conception de récepteurs radar à 77 GHz. De bons résultats ont été obtenus en se basant sur des architectures utilisant des mélangeurs actifs. Cependant l'utilisation des technologie BiCMOS se traduisait par une consommation élevée, une faible capacité d'intégration et des coûts de production importants. Récemment, l'intégration des procédés CMOS menant à l'augmentation des fréquences de transition rend ces technologies plus attractives pour les applications nécessitant un faible coût et la cointégration de plusieurs fonctions au sein d'une même puce. La littérature sur les récepteurs radars en technologie CMOS à 77 GHz montre que les architectures inspirées par les technologies BiCMOS ne sont pas pertinentes pour cette application. Le but de cette thèse et de montrer que l'utilisation de techniques propres aux technologie CMOS comme l'échantillonnage et l'utilisation de portes logiques permet d'obtenir de très bonnes performances. Dans ce travail, deux nouvelles architectures de récepteurs radars basées sur le principe d'échantillonnage sont proposées. La première architecture est basée sur un mélangeur passif échantillonné qui permet d'obtenir un très bon compromis bruit/linéarité. La seconde exploite les propriétés des mélangeurs sous-échantillonnés afin utiliser une fréquence d'OL trois fois inférieure à la fréquence RF offrant ainsi de très intéressantes simplifications au niveau de la chaîne de distribution du signal d'OL du récepteur. Le contexte de cette étude est expliqué dans le 1er chapitre qui présente les exigences de conception liées à l'application radar et fourni une analyse de l'état de l'art des récepteurs à 77 GHZ. Le chapitre suivant décrit le principe de fonctionnement et l'implémentation d'un mélangeur échantillonné à 77 GHz en technologie CMOS 28- nm FDSOI. Une topologie de mélangeur sous-échantillonné utilisant une fréquence d'OL de 26 GHz pour convertir des signaux RF autour de 77 GHz est ensuite détaillée dans le chapitre 3. Le chapitre 4 conclut cette étude en détaillant l'intégration des mélangeurs étudiés dans les chapitres précédents avec un amplificateur faible bruit dans différents récepteurs radars. Ces architectures de récepteurs basées sur l'échantillonnage sont ensuite comparées entre elles et avec l'état de l'art montrant ainsi leurs avantages et inconvénients. Les résultats de cette comparaison confirment l'intérêt des techniques d'échantillonnage pour la conversion de fréquence dans le cadre de l'application radar.With its ability to detect distant targets under harsh visibility conditions, the 77 GHz automotive radar plays a key role in driving safety. Using mm-wave frequencies allow a good range resolution, a better circuit integration and a wide modulation bandwidth. This is also a challenge for circuit designers who must fulfill stringent requirements especially on the receiver front-end. First 77 GHz radar receivers were manufactured with SiGe BiCMOS processes benefiting from the high transition frequency and high breakdown voltage of Hetero-junction Bipolar Transistors (HBT). Good results have been achieved with active-mixer-based architectures, but these technologies suffer from high power consumptions, limited integration capacity and large production cost. More recently, the scaling down of CMOS processes (coming together with the increase of the transition frequency of the transistors) makes CMOS a good candidate for 77 GHz circuit design, especially when cost target requires single chip solutions. The literature related to CMOS radar receivers highlights that receivers based on BiCMOS architectures generally show poor performances. The aim of this work is to demonstrate that using CMOS specific technics such as sampling and the use of high-speed digital gates should enhance the performance of the receivers. In this work, two innovative radar receiver architectures based on the sampling principle are proposed. The first one shows that this principle can be extended to millimeter wave frequencies to benefit from a very good noise/linearity trade-off. While the second one uses this principle to converts a 77 GHz RF signal by using a 26 GHz LO frequency thus simplifying the LO distribution chain of the receiver. The background of this study is introduced in the chapter 1 presenting the design trade-off related to the 77 GHz radar receiver and provides a review of the existing solutions. The following chapter describes the sampling mixer principle and the implementation of a 77 GHz sampling mixer in 28-nm FDSOI CMOS technology. Then, a sub- sampling mixer topology allowing to convert an RF signal around 77 GHz using a 26 GHz LO frequency is detailed in the chapter 3. The chapter 4 draws the conclusion of this study by showing the implementation of the two proposed sampling-based mixers with a low noise amplifier in 77 GHz front ends. These receiver architectures are compared with the state of the art highlighting the strengths and weaknesses of the proposed solutions. The results of this study demonstrates that using sampling for down conversion can be convenient to address millimeter-wave frequency applications

A reconfigurable low-voltage and low-power millimeter-wave dual-band mixer in 65-nm CMOS

ABSTRACT: In this paper, we propose, investigate, and demonstrate a reconfigurable low-voltage and low-power millimeter-wave mixer in a 65-nm CMOS, which can be switched as either a subharmonic mixer (SHM) or a fundamental mixer (FM) for the dual-band applications. Based on a modified Gilbert mixer topology, the proposed CMOS mixer can operate at a low supply voltage and low local oscillator (LO) pumping power while providing good performance in both SHM and FM modes. To the best of our knowledge, this is the first reported Gilbert SHM based on the stacked switching quads in a low-voltage CMOS technology. Under 1-V supply voltage and -3-dBm LO pumping power, the measured conversion gain (CG) of the proposed CMOS mixer is -4.8 ± 1.5 dB from 34 to 56 GHz and -0.1 ± 1.5 dB from 17 to 43 GHz in the SHM and FM modes, respectively. The measured double-sideband (DSB) noise figure (NF) is 18.5-20 dB from 37 to 49 GHz and 12.4-14 dB from 17 to 35 GHz in the SHM and FM modes, respectively. The measured input third-order intercept point (IIP3) is 2.9 and 3.4 dBm, respectively, for the SHM and FM modes at the LO frequency of 22 GHz. In addition, the total dc power consumption of the proposed mixer including output buffers is 7 mW in both the operation modes

A Direct Carrier I/Q Modulator for High-Speed Communication at D-Band Using 130 nm SiGe BiCMOS Technology

This paper presents a 110-170 GHz direct conversion I/Q modulator realized in 130 nm SiGe BiCMOS technology with ft/fmax values of 250 GHz/ 370 GHz. The design is based on double-balanced Gilbert mixer cells with on-chip quadrature LO phase shifter and RF balun. In single-sideband operation, the modulator exhibits up to 9.5 dB conversion gain and has measured 3 dB IF bandwidth of 12 GHz. The measured image rejection ratio and LO to RF isolation are as high as 20 dB and 31 dB respectively. Meas-ured input P1dB is -17 dBm at 127 GHz output. The DC power con-sumption is 53 mW. The active chip area is 620 μm× 480 μm in-cluding the RF and LO baluns. The circuit is capable of transmit-ting more than 12 Gbit/s QPSK signal

Design and Analysis of Low-power Millimeter-Wave SiGe BiCMOS Circuits with Application to Network Measurement Systems

Interest in millimeter (mm-) wave frequencies covering the spectrum of 30-300 GHz has been steadily increasing. Advantages such as larger absolute bandwidth and smaller form-factor have made this frequency region attractive for numerous applications, including high-speed wireless communication, sensing, material science, health, automotive radar, and space exploration. Continuous development of silicon-germanium heterojunction bipolar transistor (SiGe HBT) and associated BiCMOS technology has achieved transistors with fT/fmax of 505/720 GHz and integration with 55 nm CMOS. Such accomplishment and predictions of beyond THz performance have made SiGe BiCMOS technology the most competitive candidate for addressing the aforementioned applications. Especially for mobile applications, a critical demand for future mm-wave applications will be low DC power consumption (Pdc), which requires a substantial reduction of supply voltage and current. Conventionally, reducing the supply voltage will lead to HBTs operating close to or in the saturation region, which is typically avoided in mm-wave circuits due to expectated performance degradation and often inaccurate models. However, due to only moderate speed reduction at the forward-biased base-collector voltage (VBC) up to 0.5 V and the accuracy of the compact model HICUM/L2 also in saturation, low-power mm-wave circuits with SiGe HBTs operating in saturation offer intriguing benefits, which have been explored in this thesis based on 130 nm SiGe BiCMOS technologies: • Different low-power mm-wave circuit blocks are discussed in detail, including low-noise amplifiers (LNAs), down-conversion mixers, and various frequency multipliers covering a wide frequency range from V-band (50-75 GHz) to G-band (140-220 GHz). • Aiming at realizing a better trade-off between Pdc and RF performance, a drastic decrease in supply voltage is realized with forward-biased VBC, forcing transistors of the circuits to operate in saturation. • Discussions contain the theoretical analysis of the key figure of merits (FoMs), topology and bias selection, device sizing, and performance enhancement techniques. • A 173-207 GHz low-power amplifier with 23 dB gain and 3.2 mW Pdc, and a 72-108 GHz low-power tunable amplifier with 10-23 dB gain and 4-21 mW Pdc were designed. • A 97 GHz low-power down-conversion mixer was presented with 9.6 dB conversion gain (CG) and 12 mW Pdc. • For multipliers, a 56-66 GHz low-power frequency quadrupler with -3.6 dB peak CG and 12 mW Pdc, and a 172-201 GHz low-power frequency tripler with -4 dB peak CG and 10.5 mW Pdc were realized. By cascading these two circuits, also a 176-193 GHz low-power ×12 multiplier was designed, achieving -11 dBm output power with only 26 mW Pdc. • An integrated 190 GHz low-power receiver was designed as one receiving channel of a G-band frequency extender specifically for a VNA-based measurement system. Another goal of this receiver is to explore the lowest possible Pdc while keeping its highly competitive RF performance for general applications requiring a wide LO tuning range. Apart from the low-power design method of circuit blocks, the careful analysis and distribution of the receiver FoMs are also applied for further reduction of the overall Pdc. Along this line, this receiver achieved a peak CG of 49 dB with a 14 dB tunning range, consuming only 29 mW static Pdc for the core part and 171 mW overall Pdc, including the LO chain. • All designs presented in this thesis were fabricated and characterized on-wafer. Thanks to the accurate compact model HICUM/L2, first-pass access was achieved for all circuits, and simulation results show excellent agreement with measurements. • Compared with recently published work, most of the designs in this thesis show extremely low Pdc with highly competitive key FoMs regarding gain, bandwidth, and noise figure. • The observed excellent measurement-simulation agreement enables the sensitivity analysis of each design for obtaining a deeper insight into the impact of transistor-related physical effects on critical circuit performance parameters. Such studies provide meaningful feedback for process improvement and modeling development.:Table of Contents Kurzfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of symbols and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Technology 7 2.1 Fabrication Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 SiGe HBT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 B11HFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 SG13G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 SG13D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Commonly Used Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Grounded-sidewall-shielded microstrip line . . . . . . . . . . . . . . . . . . 12 2.2.2 Zero-impedance Transmission Line . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3.1 Active Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3.2 Passive Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Low-power Low-noise Amplifiers 25 3.1 173-207 GHz Ultra-low-power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Bias Dependency of the Small-signal Performance . . . . . . . . . . . . . 27 3.1.2.1 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2.2 Bias vs Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.2.3 Bias vs Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2.4 Bias vs Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.3 Bias selection and Device sizing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.1 Bias Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.4 Performance Enhancement Technologies . . . . . . . . . . . . . . . . . . . 41 3.1.4.1 Gm-boosting Inductors . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.4.2 Stability Enhancement . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4.3 Noise Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Circuit Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.1 Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.2 Inductors Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.5.3 Dual-band Matching Network . . . . . . . . . . . . . . . . . . . 48 3.1.5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.6 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 72-108 GHz Low-Power Tunable Amplifier . . . . . . . . . . . . . . . . . . . . . . 55 3.2.1 Configuration, Sizing, and Bias Tuning Range . . . . . . . . . . . . . . . . 55 3.2.2 Regional Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.1 Impedance Variation . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.2 Regional Matching Network Design . . . . . . . . . . . . . . . . 60 3.2.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4 Low-power Down-conversion Mixers 73 4.1 97 GHz Low-power Down-conversion Mixer . . . . . . . . . . . . . . . . . . . . . 74 4.1.1 Mixer Design and Implementation . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.1 Mixer Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.2 Bias Selection and Device Sizing . . . . . . . . . . . . . . . . . . 77 4.1.1.3 Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 Low-power Multipliers 87 5.1 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2 56-66 GHz Low-power Frequency Quadrupler . . . . . . . . . . . . . . . . . . . . 89 5.3 172-201 GHz Low-power Frequency Tripler . . . . . . . . . . . . . . . . . . . . . 93 5.4 176-193 GHz Low-power ×12 Frequency Multiplier . . . . . . . . . . . . . . . . . 96 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6 Low-power Receivers 101 6.1 Receiver Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LO Chain (×12) Integrated 190 GHz Low-Power Receiver . . . . . . . . . . . . . 104 6.2.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2 Low-power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.3 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.1 LNA and LO DA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.2 Tunable Mixer and IF BA . . . . . . . . . . . . . . . . . . . . . 111 6.2.3.3 65 GHz (V-band) Quadrupler . . . . . . . . . . . . . . . . . . . 116 6.2.3.4 G-band Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.4 Receiver Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . 123 6.2.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7 Conclusions 133 7.1 Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Bibliography 135 List of Figures 149 List of Tables 157 A Derivation of the Gm 159 A.1 Gm of standard cascode stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.2 Gm of cascode stage with Lcas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 A.3 Gm of cascode stage with Lb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 B Derivation of Yin in the stability analysis 163 C Derivation of Zin and Zout 165 C.1 Zin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 C.2 Zout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 D Derivation of the cascaded oP1dB 169 E Table of element values for the designed circuits 17

Millimeter-Wave and Terahertz Transceivers in SiGe BiCMOS Technologies

This invited paper reviews the progress of silicon–germanium (SiGe) bipolar-complementary metal–oxide–semiconductor (BiCMOS) technology-based integrated circuits (ICs) during the last two decades. Focus is set on various transceiver (TRX) realizations in the millimeter-wave range from 60 GHz and at terahertz (THz) frequencies above 300 GHz. This article discusses the development of SiGe technologies and ICs with the latter focusing on the commercially most important applications of radar and beyond 5G wireless communications. A variety of examples ranging from 77-GHz automotive radar to THz sensing as well as the beginnings of 60-GHz wireless communication up to THz chipsets for 100-Gb/s data transmission are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of SiGe TRX performance

SILICON TERAHERTZ ELECTRONICS: CIRCUITS AND SYSTEMS FOR FUTURE APPLICATIONS

The terahertz frequency bands are gaining increasing attention these days for the potential applications in imaging, sensing, spectroscopy, and communication. These applications can be used in a wide range of fields, such as military, security, biomedical analysis, material science, astronomy, etc. Unfortunately, utilizing these frequency bands is very challenging due to the notorious ”terahertz gap”. Consequently, current terahertz systems are very bulky and expensive, sometimes even require cryogenic conditions. Silicon terahertz electronics now becomes very attractive, since it can achieve significantly lower cost and make portable consumer terahertz devices feasible. However, due to the limited device fmax and low breakdown voltage, signal generation and processing on silicon platform in this frequency range is challenging. This thesis aims to tackle these challenges and implement high-performance terahertz systems. First of all, the devices are investigated under the terahertz frequency range and optimum termination conditions for maximizing the efficacy of the devices is derived. Then, novel passive surrounding networks are designed to provide the devices with the optimal termination conditions to push the performances of the terahertz circuit blocks. Finally, the high-performance circuit blocks are used to build terahertz systems, and system-level innovations are also proposed to push the state of the art forward. In Chapter 2, using a device-centric bottom-up design method, a 210-GHz harmonic oscillator is designed. With the parasitic tuning mechanism, a wide frequency tuning range is achieved without using lossy varactors. A passive network based on the return-path gap coupler and self-feeding structure is also designed to provide optimal terminations for the active devices to maximize the harmonic power generation. Fabricated with a 0.13-um SiGe BiCMOS process, the oscillator is highly compact with a core size of only 290x95 um2. The output frequency can be tuned from 197.5 GHz to 219.7 GHz, which is around 10.6% compared to the center frequency. It also achieves a peak output power and dc-to-RF efficiency of 1.4 dBm and 2.4%, respectively. The measured output phase noise at 1 MHz offset is -87.5 dBc/Hz. The high power, wide tuning range, low phase noise, as well as compact size, make this oscillator very suitable for terahertz systems integration. In Chapter 3, the design of a 320-GHz fully-integrated terahertz imaging system is described. The system is composed of a phase-locked high-power transmitter and a coherent high-sensitivity subharmonic-mixing receiver, which are fabricated using a 0.13-um SiGe BiCMOS technology. To enhance the imaging sensitivity, a heterodyne coherent detection scheme is utilized. To obtain frequency coherency, fully-integrated phase-locked loops are implemented on both the transmitter and receiver chips. According to the measurement, consuming a total dc power of 605 mW, the transmitter chip achieves a peak radiated power of 2 mW and a peak EIRP of 21.1 dBm. The receiver chip achieves an equivalent incoherent responsivity of more than 7.26 MV/W and a sensitivity of 70.1 pW under an integration bandwidth of 1 kHz, with a total dc power consumption of 117 mW. The achieved sensitivity with this proposed coherent imaging transceiver is around ten times better compared with other state-of-the-art incoherent imagers. In Chapter 4, a spatial-orthogonal ASK transmitter architecture for high-speed terahertz wireless communication is presented. The self-sustaining oscillator-based transmitter architecture has an ultra-compact size and excellent power efficiency. With the proposed high-speed constant-load switch, significantly reduced modulation loss is achieved. Using polarization diversity and multi-level modulation, the throughput is largely enhanced. Array configuration is also adopted to enhance the link budget for higher signal quality and longer communication range. Fabricated in a 0.13-um SiGe BiCMOS technology, the 220-GHz transmitter prototype achieves an EIRP of 21 dBm and dc-to- THz-radiation efficiency of 0.7% in each spatial channel. A 24.4-Gb/s total data rate over a 10-cm communication range is demonstrated. With an external Teflon lens system, the demonstrated communication range is further extended to 52 cm. Compared with prior art, this prototype demonstrates much higher transmitter efficiency. In Chapter 5, an entirely-on-chip frequency-stabilization feedback mechanism is proposed, which avoids the use of both frequency dividers and off-chip references, achieving much lower system integration cost and power consumption. Using this mechanism, a 301.7-to-331.8-GHz source prototype is designed in a 0.13-um SiGe BiCMOS technology. According to the measurement, the source consumes a dc power of only 51.7 mW. The output phase noise is -71.1 and -75.2 dBc/Hz at 100 kHz and 1 MHz offset, respectively. A -13.9-dBm probed output power is also achieved. Overall, the prototype source demonstrates the largest output frequency range and lowest power consumption while achieving comparable phase noise and output power performances with respect to the state of the art. All the designs demonstrated in this thesis achieve good performances and push the state of the art forward, paving the way for implementation of more sophisticated terahertz circuits and systems for future applications