Digital Radio Encoding and Power Amplifier Design for Multimode and Multiband Wireless Communications

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals

Amplitude and phase modulation techniques for an asymmetric multi-level outphasing transmitter

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 93-95).New techniques for improving outphasing transmitters show potential of breaking the traditional linearity-efficiency trade-off by using highly efficient non-linear switching Power Amplifiers (PAs). This work focuses on two of the main building blocks of modem outphasing systems, the power supply switching network and the phase modulator. Both are ubiquitous building blocks in modern RF transceivers, and both are especially critical in Asymmetric Multilevel Outphasing (AMO) systems. A design of the power supply network and control scheme is proposed for an implementation in mm-wave operating frequencies as part of a complete transmitter in 45nm SOI CMOS utilizing four discrete power supplies and achieving data rates of up to 4GS/s. The design includes analysis and simulation of the control signal data path requirements for optimal system operation as well as switch optimization and effects of the driving strength on overall system performance. A new design concept is proposed for a phase modulator utilizing the phase shifthing capabilities of a resonant tank and the ability to seperately control the circuit properties via its components. A prototype in 65nm CMOS achieves 12 bits of resolution, with an Effective Number Of Bits (ENOB) of 10.2 bits and very fast settling time of less than 5 carrier cycles. The chip is also tested as a stand alone transmitter showing an EVM of less than 5% for 8-PSK modulation at maximum data rate, meeting the requirements for operation at the Medical Implant Communication Services (MICS) band.by Gilad Yahalom.S.M

Digitally-Assisted RF IC Design Techniques for Reliable Performance

Semiconductor industries have competitively scaled down CMOS devices to attain benefits of low cost, high performance, and high integration density in digital integrated circuits. On the other hand, deep scaled technologies inextricably accompany a large process variation, supply voltage scaling, and reduction in breakdown voltages of transistors. When it comes to RF/analog IC design, CMOS scaling adversely affects its reliability due to large performance variation and limited linearity. For addressing the issues related to variations and linearity, this research proposes the following digitally-assisted RF circuit design techniques: self-calibration system for RF phase shifters and wide dynamic range LNAs. Due to PVT variations in scaled technologies, RF phase shifter design becomes more challenging with device scaling. In the proposed self-calibration topology, we devised a novel phase sensing method and a pulsewidth-to-digital converter. The feedback controller is also designed in digital domain, which is robust to PVT variations. These unique techniques enable a sensing/control loop tolerant to PVT variations. The self-calibration loop was applied to a 7 to 13GHz phase shifter. With the calibration, the estimated phase error is less than 2 degrees. To overcome the linearity issue in scaled technologies, a digitally-controlled dual-mode LNA design is presented. A narrowband (5.1GHz) and a wideband (0.8 to 6GHz) LNA can be toggled between high-gain and high-linearity modes by digital control bits according to the input signal power. A compact design, which provides negligible performance degradation by additional circuitry, is achieved by sharing most of the components between the two operation modes. The narrowband and the wideband LNA achieves an input-referred P1dB of -1.8dBm and +4.2dBm, respectively