A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

A 64-Channel 965-μW Neural Recording SoC with UWB Wireless Transmission in 130-nm CMOS

This brief presents a 64-channel neural recording system-on-chip (SoC) with a 20-Mb/s wireless telemetry. Each channel of the analog front end consists of a low-noise bandpass amplifier, featuring a noise efficiency factor of 3.11 with an input-referred noise of 5.6 μVrms in a 0.001- to 10-kHz band and a 31.25-kSps 6-fJ/conversion-step 10-bit SAR analog-to-digital converter. The recorded signals are multiplexed in the digital domain and transmitted via an 11.7% efficiency pulse-position modulation ultrawideband transmitter, reaching a transmission range in excess of 7.5 m. The chip has been fabricated in a 130-nm CMOS process, measures 25 mm2, and dissipates 965 μW from a 0.5-V supply. This SoC features the lowest power per channel (15 μW) and the lowest energy per bit (48.2 pJ) among state-of-the-art wireless neural recording systems with a number of channels larger than 32. The proposed circuit is able to transmit the raw neural signal in a large bandwidth (up to 10 kHz) without performing any data compression or losing vital information, such as local field potentials

A 100MHz CMOS wideband IF amplifier

When the data rates of communication systems increase, wideband IF amplifiers are needed. It is also possible to use a single wideband intermediate frequency (IF) amplifier for a radio band with several narrow-band channels of varying strengths. The linearity is then critical, if intermodulation products are not to disturb weak channels. We try to find a topology for this new amplifier application, suitable for integration in a standard CMOS process. To get low distortion, we use an output stage with high linearity, which is further linearized by feedback in a double-nested Miller configuration. A 0.8-μm standard CMOS IF amplifier design with low distortion up to 20 MHz is presented

Status of a DEPFET pixel system for the ILC vertex detector

We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix steering and the CURO II chip for readout. The system development has been driven by the final ILC requirements which above all demand a detector thinned to 50 micron and a row wise read out with line rates of 20MHz and more. The targeted noise performance for the DEPFET technology is in the range of ENC=100 e-. The functionality of the system has been demonstrated using different radioactive sources in an energy range from 6 to 40keV. In recent test beam experiments using 6GeV electrons, a signal-to-noise ratio of S/N~120 has been achieved with present sensors being 450 micron thick. For improved DEPFET systems using 50 micron thin sensors in future, a signal-to-noise of 40 is expected.Comment: Invited poster at the International Symposium on the Development of Detectors for Particle, AstroParticle and Synchrotron Radiation Experiments, Stanford CA (SNIC06) 6 pages, 12 eps figure

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

A design tool for high-resolution high-frequency cascade continuous- time Σ∆ modulators

Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, SpainThis paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade Σ∆ modulators. The salient features of this methodology ar e: (a) flexible behavioral modeling for optimum accuracy- efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; a nd (c) mixed knowledge-based and optimization-based architec- tural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Σ∆ modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y Educación TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec

Performance Analysis of MEMS Based Oscillator for High Frequency Wireless Communication Systems

The frequency oscillator is a basic component found in many electrical, electronic, and communications circuits and systems. Oscillators come in a variety of shapes and sizes, depending on the frequency range employed in a given application. Some applications need oscillators that generate low frequencies and other applications need oscillators that generate extremely high and high frequencies. As a result of the expansion and speed of modern technologies, new oscillators appeared that operating at extremely high frequencies. Most wireless communication systems are constrained in their performance by the accuracy and stability of the reference frequency. Because of its compatibility with silicon, micro-electro-mechanical system (MEMS) is the preferred technology for circuit integration and power reduction. MEMS are a rapidly evolving area of advanced microelectronics. The integration of electrical and mechanical components at the micro size is referred to as a MEMS. MEMS based oscillators have demonstrated tremendous high frequency application potential in recent years. This is owing to their great characteristics such as small size, integration of CMOS IC technology, high frequency-quality factor product, low power consumption, and cheap batch manufacturing cost. This paper's primary objective is to describe the performance of MEMS oscillator technology in high-frequency applications, as well as to discuss the challenges of developing a new MEMS oscillator capable of operating at gigahertz frequencies

OWLs: A mixed-signal ASIC for optical wire-less links in space instruments

This paper describes the design of a mixed-signal ASIC for space application and the techniques employed for radiation hardening and temperature effects compensation. The work is part of a planned long-term effort and collaboration between "Instituto de Microelectrónica de Sevilla (IMSE)", "Universidad de Sevilla (US)", and "Instituto Nacional de Técnica Aeroespacial (INTA)" aimed to consolidate a group of experienced mixed-signal space-ASIC designers. The initiative is partially funded by the Spanish National Research Program. The ASIC performs the function of an optical digital transceiver for diffuse-light intra-satellite optical communications. It has been designed in a 0.35μm CMOS technology from austriamicrosystems (ams). The chip has been manufactured and verified from a functional perspective. Radiation characterization is planned for the third quarter of 2012. Power- and temperature-stress tests, as well as life-tests are also planned for this next quarter, and will be carried out by Alter Technology TÜV Nord S.A.U. Given the previous characterization of the technology [1] and the hardening techniques employed in the design and layout, radiation is not expected to be a problem. The specified environmental limits are a pedestal hard limit of 50KRads with the goal of maximizing TID tolerance, SEU and SET LET-thresholds above 70MeV/(mg/cm2), and latchup free behavior up to the same LET limit. Concerning temperature, the specified operation range is from -90 to +125ºC, while the non-operating temperature range is from -135 to +150ºC.Ministerio de Ciencia e Innovación (MICINN) MEIGA AYA2009-14212-C05-04, AYA2008-06420-C04-0