1 research outputs found
Mitigate Parasitic Resistance in Resistive Crossbar-based Convolutional Neural Networks
Traditional computing hardware often encounters on-chip memory bottleneck on
large scale Convolution Neural Networks (CNN) applications. With its unique
in-memory computing feature, resistive crossbar-based computing attracts
researchers' attention as a promising solution to the memory bottleneck issue
in von Neumann architectures. However, the parasitic resistances in the
crossbar deviate its behavior from the ideal weighted summation operation. In
large-scale implementations, the impact of parasitic resistances must be
carefully considered and mitigated to ensure circuits' functionality. In this
work, we implemented and simulated CNNs on resistive crossbar circuits with
consideration of parasitic resistances. Moreover, we carried out a new mapping
scheme for high utilization of crossbar arrays on convolution, and a mitigation
algorithm to mitigate parasitic resistances in CNN applications. The mitigation
algorithm considers parasitic resistances as well as data/kernel patterns of
each layer to minimize the computing error in crossbar-based convolutions of
CNNs. We demonstrated the proposed methods with implementations of a 4-layer
CNN on MNIST and ResNet(20, 32, and 56) on CIFAR-10. Simulation results show
the proposed methods well mitigate the parasitic resistances in crossbars. With
our methods, modern CNNs on crossbars can preserve ideal(software) level
classification accuracy with 6-bit ADCs and DACs implementation.Comment: Proceedings of ACM Journal on Emerging Technologies in Computing
(JETC) SI: Nanoelectronic Device, Circuit, Architecture Design. arXiv admin
note: text overlap with arXiv:1810.0222