Low-voltage low-power continuous-time delta-sigma modulator designs

Ph.DDOCTOR OF PHILOSOPH

Bandpass delta-sigma modulators for radio receivers

This thesis concerns discrete-time (DT) bandpass (BP) ΔΣ modulators targeted for intermediate frequency (IF) analog-to-digital (A/D) conversion in radio receivers. The receiver architecture adopted has to be capable of operating with different radio frequencies, channel bandwidths, and modulation techniques. This is necessary in order to achieve an extensive operating area and the possibility of utilizing a local mobile phone standard or a standard suitable for a specific service. The digital IF receiver is a good choice for a multi-mode and multi-band mobile phone receiver, because the signal demodulation and channel filtering are performed in the digital domain. This increases the flexibility of the receiver and relieves the design of the baseband part, but an A/D conversion with high dynamic range and low power dissipation is required. BP ΔΣ modulators are capable of converting a high-frequency narrow band signal and are therefore suitable for signal digitization in an IF receiver. First, the theory of BP ΔΣ modulators is introduced. It has been determined that resonators are the most critical circuit blocks in the implementation of a high performance BP ΔΣ modulator. Different DT resonator topologies are studied and a double-delay (DD) resonator is found to be the best candidate for a high quality resonator. A new DD switched-capacitor (SC) resonator structure has been designed. Furthermore, two evolution versions of the designed SC resonator are presented and their nonidealities are analyzed. The three designed DD SC resonator structures are a main point of the thesis, together with the experimental results. Five different DT BP ΔΣ modulator circuit structures have been implemented and measured. All three of the designed SC resonators are used in the implemented circuits. The experimental work consists of both single-bit and multi-bit structures, as well as both single-loop and cascade architectures. The circuits have been implemented with a 0.35 μm (Bi)CMOS technology and operate with a 3.0 V supply. The measured maximum signal-to-noise-and-distortion ratios (SNDRs) are 78 dB over 270 kHz (GSM), 75 dB over 1.25 MHz (IS-95), 69 dB over 1.762 MHz (DECT), and 48 dB over 3.84 MHz (WCDMA) bandwidths using a 60 MHz IF signal.reviewe

Efficient Hybrid Continuous-Time/Discrete-Time Cascade Modulators for Wideband Applications

This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all ΣΔ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid ΣΔ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4-bit) cascade ΣΔ modulator is discussed to illustrate the potential benefits of the presented approachMinisterio de Economía y Competitividad TEC2010-14825/MI

A survey on continuous-time modulators : theory, designs and implementations

Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm

Comparison of Simulation Methods of Single and Multi-Bit Continuous Time Sigma Delta Modulators

Continuous time Sigma Delta Modulators (CT ΣΔMs) are a type of analog to digital converter (ADC) that are used in mixed signal systems to convert analog signals into digital signals. ADCs typically require antialiasing filter; however antialiasing filters are inherent in CT ΣΔMs, and therefore they require less circuitry and less power than other ADC architectures that require separate antialiasing filters. As a result, CT ΣΔM ADC architectures are preferred in many mixed signal electronic applications. Because of the mixed signal nature of CT ΣΔMs, they can be difficult to simulate. In this thesis, various methods for simulating single-bit and multi-bit CT ΣΔMs are developed and these simulations include the bilinear transform or trapezoidal integration, impulse invariance transform, midpoint integration, Simpson’s rule, delta transform or Euler’s forward integration rule and Simulink modeling. These methods are compared with respect to speed which is given by the total simulation time, accuracy which is given by the signal to noise ratio (SNR) value and the simplicity of the simulation method. The CT ΣΔMs have been extended from first order up to fifth order with one, two and three bit quantizers. Also, the frequency domain analysis is done for all the orders of CT ΣΔMs. The results show that the numerical integration methods are more accurate and faster than Simulink. However, CT ΣΔM simulations using Simulink are simpler because of the availability of the required blocks in Simulink. The overall comparison shows that the numerical integration methods can perform better than Simulink models. The frequency domain analysis proves the correctness of the use of numerical integration methods for CT ΣΔM simulations

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Design of a Cost-Efficient Reconfigurable Pipeline ADC

Power budget is very critical in the design of battery-powered implantable biomedical instruments. High speed, high resolution and low power usually cannot be achieved at the same time. Therefore, a tradeoff must be made to compromise every aspect of those features. As the main component of the bioinstrument, high conversion rate, high resolution ADC consumes most of the power. Fortunately, based on the operation modes of the bioinstrument, a reconfigurable ADC can be used to solve this problem. The reconfigurable ADC will operate at 10-bit 40 MSPS for the diagnosis mode and at 8-bit 2.5 MSPS for the monitor mode. The ADC will be completely turned off if no active signal comes from sensors or if an off command is received from the antenna. By turning off the sample hold stage and the first two stages of the pipeline ADC, a significant power saving is achieved. However, the reconfigurable ADC suffers from two drawbacks. First, the leakage signals through the extra off-state switches in the third stage degrade the performance of the data converter. This situation tends to be even worse for high speed and high-resolution applications. An interference elimination technique has been proposed in this work to solve this problem. Simulation results show a significant attenuation of the spurious tones. Moreover, the transistors in the OTA tend to operate in weak inversion region due to the scaling of the bias current. The transistor in subthreshold is very slow due to the small transit frequency. In order to get a better tradeoff between the transconductance efficiency and the transit frequency, reconfigurable OTAs and scalable bias technique are devised to adjust the operating point from weak inversion to moderate inversion. The figure of merit of the reconfigurable ADC is comparable to the previously published conventional pipeline ADCs. For the 10-bit, 40 MSPS mode, the ADC attains a 56.9 dB SNDR for 35.4 mW power consumption. For the 8-bit 2.5 MSPS mode, the ADC attains a 49.2 dB SNDR for 7.9 mW power consumption. The area for the core layout is 1.9 mm2 for a 0.35 micrometer process