Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd

메모리 인터페이스를 위한 20Gbps급 직렬화 송수신기 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 정덕균.Various types of serial link for current and future memory interface are presented in this thesis. At first, PHY design for commercial GDDR3 memory is proposed. GDDR3 PHY is consists of read path, write path, command path. Write path and command path calibrate skew by using VDL (Variable delay line), while read path calibrates skew by using DLL (Delay locked loop) and VDL. There are four data channels and one command/address channel. Each data channel consists of one clock signal (DQS) and eight data signals (DQ). Data channel operates in 1.2Gbps (1.08Gbps~1.2Gbps), and command/address channel operates 600Mbps (540Mbps~600Mbps). In particular, DLL design for high speed and for SSN (simultaneous switching noise) is concentrated in this thesis. Secondly, serial link design for silicon photonics is proposed. Silicon photonics is the strongest candidate for next generation memory interface. Modulator driver for modulator, TIA (trans-impedance amplifier) and LA (limiting amplifier) for photo diode design are discussed. It operates above 12.5Gbps but it consumes much power 7.2mW/Gbps (transmitter core), 2mW/Gbps (receiver core) because it is connected with optical device which has large parasitic capacitance. Overall receiver which includes CDR (clock and data recovery) is also implemented. Many chips are fabricated in 65nm, 0.13um CMOS process. Finally, electrical serial link for 20Gbps memory link is proposed. Overall architecture is forwarded clocking architecture, and is very simple and intuitive. It does not need additional synchronizer. This open loop delay matched stream line receiver finds optimum sampling point with DCDL (Digitally controlled delay line) controller and expects to consume low power structurally. Only two phase half rate clock is transmitted through clock channel, but half rate time interleaved way sampling is performed by aid of initial value settable PRBS chaser. A CMOS Chip is fabricated by 65nm process and it occupies 2500um x 2500um (transceiver). It is expected that about 2.6mW(2.4mW)/Gbps (transmitter), 4.1mW(2.7mW)/Gbps (receiver). Power consumption improvement is expected in advanced process.ABSTRACT I CONTENTS V LIST OF FIGURES VII LIST OF TABLES XII CHAPTER 1 INTRODUCTION １ 1.1 MOTIVATION １ 1.2 THESIS ORGANIZATION １０ CHAPTER 2 A SERIAL LINK PHY DESIGN FOR GDDR3 MEMORY INTERFACE 11 2.1 INTRODUCTION 11 2.2 GDDR3 MEMORY INTERFACE ARCHITECTURE 12 2.2.1 READ PATH ARCHITECTURE 15 2.2.2 WRITE PATH ARCHITECTURE 17 2.2.3 COMMAND PATH ARCHITECTURE 19 2.3 DLL DESIGN FOR MEMORY INTERFACE 20 2.3.1 SSN(SIMULTANEOUS SWITCHING NOISE) 20 2.3.2 DLL ARCHITECTURE 21 2.3.3 VOLTAGE CONTROLLED DELAY LINE (VCDL) 22 2.3.4 HYSTERESIS COARSE LOCK DETECTOR (HCLD) 23 2.3.5 DYNAMIC PHASE DETECTOR AND CHARGE PUMP 26 2.4 SIMULATION RESULT 29 2.5 CONCLUSION 32 CHAPTER 3 OPTICAL FRONT-END SERIAL LINK DESIGN FOR 20 GBPS MEMORY INTERFACE 35 3.1 SILICON PHOTONICS INTRODUCTION 35 3.2 OPTICAL FRONT-END TRANSMITTER DESIGN 45 3.2.1 MODULATOR DRIVER REQUIREMENTS 46 3.2.2 MODULATOR DRIVER DESIGN - CURRENT MODE DRIVER 47 3.2.3 MODULATOR DRIVER DESIGN - CURRENT MODE DRIVER 50 3.3 OPTICAL FRONT-END RECEIVER DESIGN 55 3.3.1 OPTICAL RECEIVER BACK END REQUIREMENTS 56 3.3.2 OPTICAL RECEIVER BACK END DESIGN – TIA 57 3.3.3 OPTICAL RECEIVER BACK END DESIGN – LA, DRIVER 63 3.3.4 OPTICAL RECEIVER BACK END DESIGN – CDR 66 3.4 MEASUREMENT AND SIMULATION RESULTS 70 3.4.1 MEASUREMENT AND SIMULATION ENVIRONMENTS 70 3.4.2 OPTICAL TX FRONT END MEASUREMENT AND SIMULATION 74 3.4.3 OPTICAL RX FRONT END MEASUREMENT AND SIMULATION 77 3.4.4 OPTICAL RX BACK END SIMULATION 79 3.4.5 OPTICAL-ELECTRICAL OVERALL MEASUREMENTS 80 3.4.6 DIE PHOTO AND LAYOUT 82 3.5 CONCLUSION 86 CHAPTER 4 ELECTRICAL FRONT-END SERIAL LINK DESIGN FOR 20GBPS MEMORY INTERFACE 87 4.1 INTRODUCTION 87 4.2 CONVENTIONAL ELECTRICAL FRONT-END HIGH SPEED SERIAL LINK ARCHITECTURES 90 4.3 DESIGN CONCEPT AND PROPOSED SERIAL LINK ARCHITECTURE – OPEN LOOP DELAY MATCHED STREAM LINED RECEIVER. 95 4.3.1 PROPOSED OVERALL ARCHITECTURE 95 4.3.2 DESIGN CONCEPT 97 4.3.3 PROPOSED PROTOCOL AND LOCKING PROCESS 100 4.4 OPTIMUM POINT SEARCH ALGORITHM BASED DCDL CONTROLLER DESIGN 102 4.5 DCDL (DIGITALLY CONTROLLED DELAY LINE) DESIGN 112 4.6 DFE (DECISION FEEDBACK EQUALIZER) AND OTHER BLOCKS DESIGN 115 4.7 SIMULATION RESULTS 117 4.8 POWER EXPECTATION AND CHIP LAYOUT 122 4.9 CONCLUSION 124 CHAPTER 5 CONCLUSION 126 BIBLIOGRAPHY 128Docto

Clock multiplication techniques for high-speed I/Os

Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored. First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz. Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB. Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively

Experimental tools for quantum networking operations with single photons and sinlge ions

One promising approach for future quantum networks is the combination of strings of trapped ions as quantum-information processors with entangled photon pairs produced by spontaneous parametric down conversion (SPDC) to establish quantum communication links between distant processing units. This work reports on experiments using a hybrid quantum-optics set-up, comprising two separate linear ion traps and a resonant SPDC photon-pair source. It demonstrates the controlled interaction of single entangled photon pairs with a single trapped 40Ca+ ion. Preparing the ion as polarization selective absorber in the main polarization bases allows for the reconstruction of the biphoton quantum state, manifesting the photon entanglement in the absorption process. Beyond that, the thesis documents the implementation of additional experimental tools enabling quantum state transfer experiments from photons to single ions. A dedicated narrowbandwidth laser system is set up, laser sequences are developed for state discrimination and state rotations of ion qubits, and for the creation and characterization of coherent superposition states, of particular importance for state-transfer schemes. Finally, detection efficiencies of single Raman photons emitted by an ion are characterized with a well controlled single-photon source, and absorption probabilities of single photons are determined with a calibrated laser beam, providing precise values to assess efficiencies for different transfer scenarios.Un enfoque prometedor para futuras redes cuánticas es la combinación de iones atrapados con pares de fotones entrelazados que se generan por el proceso SPDC (Spontaneous Parametric Down Conversion). Los iones atrapados se utilizarán como procesadores de información cuántica. Los pares de fotones permitirán el establecimiento de enlaces de comunicación cuántica entre unidades de procesamiento distantes. En el transcurso de este trabajo, que se situa en el marco de la óptica cuántica, se han combinado dos implementaciones experimentales independientes para la realización de un experimento híbrido. Las dos partes del experimento corresponden con dos trampas de iones lineales separadas y con una fuente de pares de fotones resonantes creados por SPDC. En este experimento se demuestra la interacción controlada de pares de fotones individuales entrelazados con un ión atrapado individual de 40Ca+. La preparación del ión como absorbente selectivo de polarización en las bases de polarización principales permite la reconstrucción del estado cuántico de los pares de fotones, manifestando así su entrelazamiento a través del proceso de absorción. Además, en la tesis presente se documenta la implementación de herramientas experimentales adicionales que permitirán experimentos de transferencia de estados cuánticos de fotones a iones individuales. Así mismo, se describe el montaje de un sistema láser acondicionado con ancho de banda estrecho. Adicionalmente, se desarrollan secuencias de láser para la discriminación y la rotación de estados de qubits de iones y, para la creación y caracterización de estados de superposición coherente, especialmente importantes para varios esquemas de transferencia de estado. Por último, se caracterizan las eficiencias de detección de fotones individuales Raman emitidos por un ión con una fuente de fotones individuales bien controlada, así como también se determinan las probabilidades de absorción de fotones individuales con una fuente láser calibrada. Los valores precisos obtenidos servirán para la evaluación de la eficiencia de diferentes esquemas de transferencia.Ein mögliches System für zukünftige Quantennetzwerke ist die Verknüpfung gefangener Ionen als Quanteninformationsprozessoren mit durch SPDC (Spontaneous Parametric Down Conversion) erzeugten verschränkten Photonenpaaren zum Aufbau von Quantenkommunikationskanälen. Diese Dissertation behandelt Experimente an einem hybriden Quantenoptikaufbau, bestehend aus zwei separaten linearen Ionenfallen und einer SPDC-Photonenpaarquelle. Sie zeigt die kontrollierte Wechselwirkung einzelner verschränkter Photonenpaare mit einem einzelnen 40Ca+ Ion. Durch Präparation des Ions als polarisationsselektiven Absorber in den drei Hauptpolarisationsbasen, wird der Zwei-Photonen-Quantenzustand rekonstruiert und somit über den Absorptionsprozess die Verschränkung der Photonenpaare nachgewiesen. Überdies dokumentiert die Arbeit die Einrichtung zusätzlicher Methoden, welche den Zustandstransfer von Photonen auf einzelne Ionen ermöglichen. Ein schmalbandiges Lasersystem wird aufgebaut, Lasersequenzen für Zustandsbestimmung und Zustandsrotationen von Ionen-Qubits und zur Erzeugung und Charakterisierung kohärenter Superpositionszustände werden entwickelt. Ferner werden mit Hilfe einer Einzelphotonenquelle Nachweiseffizienzen für einzelne, von einem Ion erzeugte, Raman-Photonen gemessen und Absorptionseffizienzen einzelner Photonen mit einer kalibrierten Laserquelle charakterisiert. Die ermittelten Werte bilden eine solide Grundlage zur Abschätzung von Erfolgswahrscheinlichkeiten geplanter Transferschemata