Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Noncontact Vital Signs Detection

Human health condition can be accessed by measurement of vital signs, i.e., respiratory rate (RR), heart rate (HR), blood oxygen level, temperature and blood pressure. Due to drawbacks of contact sensors in measurement, non-contact sensors such as imaging photoplethysmogram (IPPG) and Doppler radar system have been proposed for cardiorespiratory rates detection by researchers.The UWB pulse Doppler radars provide high resolution range-time-frequency information. It is bestowed with advantages of low transmitted power, through-wall capabilities, and high resolution in localization. However, the poor signal to noise ratio (SNR) makes it challenging for UWB radar systems to accurately detect the heartbeat of a subject. To solve the problem, phased-methods have been proposed to extract the phase variations in the reflected pulses modulated by human tiny thorax motions. Advance signal processing method, i.e., state space method, can not only be used to enhance SNR of human vital signs detection, but also enable the micro-Doppler trajectories extraction of walking subject from UWB radar data.Stepped Frequency Continuous Wave (SFCW) radar is an alternative technique useful to remotely monitor human subject activities. Compared with UWB pulse radar, it relieves the stress on requirement of high sampling rate analog-to-digital converter (ADC) and possesses higher signal-to-noise-ratio (SNR) in vital signs detection. However, conventional SFCW radar suffers from long data acquisition time to step over many frequencies. To solve this problem, multi-channel SFCW radar has been proposed to step through different frequency bandwidths simultaneously. Compressed sensing (CS) can further reduce the data acquisition time by randomly stepping through 20% of the original frequency steps.In this work, SFCW system is implemented with low cost, off-the-shelf surface mount components to make the radar sensors portable. Experimental results collected from both pulse and SFCW radar systems have been validated with commercial contact sensors and satisfactory results are shown

MMW FM-CW ground-based SAR

This paper presents the design of two ground based synthetic aperture radar (GB-SAR) systems working at 94 and 300 GHz respectively. Frequency-modulated continuous-wave (FM-CW) technique is used for both systems, being described in the first section. Afterwards the first design at 94GHz is presented, explaining its geometry of exploration and describing the architecture of the W-band radar setup. Regarding the integrated receiver system, two models of low noise (LNA) and medium power amplifiers are disclosed, presenting noise figure and S parameters curves comprising frequencies between 75 and 110 GHz (W-band). Finally the second radar setup working at 300GHz is presented, depicting the hardware block diagram and explaining the main performance parameters of the system