A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technology

Trabajo presentado al 13th DDECS celebrado en Viena del 14 al 16 de abril de 2010.This paper presents the design of a fully differential double balanced switched transconductor mixer for ZigBee applications in the 2.4GHz band. It provides programmable conversion gain by using an active load stage. The design includes RF and LO input matching networks. It has been implemented in a 90nm 1P9M CMOS process. Post-layout simulations show conversion gains of 12dB/20dB, NF of 18.9dB/18.1dB and power consumption of 4.1mW/4.4mW at high and low gain mode respectively from a 1.2V power supply. It also offers very good linearity performance.This work has been founded in part by the EC through the project SR2 - Short Range Radio (Catrene European project 2A105SR2 and Avanza I+D Spanish project TSI-020400-2008-71), the Spanish Government under project TEC2007-68072/MIC and the Spanish Regional Government of Junta de Andalucía under the project ACATEX (P09-TIC-5386).Peer Reviewe

Design of Integrated Mixer for 5G Radio Transceiver

The increased demand of high data rate, low latency and wider bandwidth is pushing the wireless communication towards higher frequencies. 3GPP (third generation partnership project) allocated NR (new radio) FR2 (frequency range 2) n257 (26.5 - 29.5 GHz) and n258 (24.25 - 27.5 GHz) bands for high-speed communication. It is challenging to achieve high linearity at higher frequencies with low supply voltage and smaller size devices. This thesis presents design, implementation and simulation results of integrated downconversion mixer for modular 5G radio transceiver. The first stage downconversion mixer, implemented in GF FDSOI 22 nm process will be used in super-heterodyne double downconversion transceiver, operates at 28 GHz input frequency and provides 6-7 GHz intermediate frequency (IF). The pre-layout and post-layout simulation results of double-balanced mixer topologies optimized for high linearity are compared in terms of conversion gain (CG), input third-order intercept point (IIP3), double sideband (DSB) noise figure (NF), LO-to-IF leakage,and dc power consumption. The mixer topologies, including Gilbert cell and variants of Gilbert cell with resistive and inductive degeneration, and mixer with transformer input, show trade-off between conversion gain, linearity, dc power consumption, and area. Under 0.8-V supply voltage, the transformer input mixer achieves highest IIP3 of +16.34 dBm while dc power consumption including LO buffer is 5.7 mW and NFdsb is 13.7 dB

Design and implementation of linearized CMOS mixer for RF application.

Au-Yeung Chung-Fai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 85-91).Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiContents --- p.ivChapter Chapter 1 --- Introduction --- p.1Chapter Chapter 2 --- Basic Theory of Mixer --- p.6Chapter 2.1 --- Definition of mixer's electrical parameters --- p.8Chapter 2.2.1 --- Conversion gain --- p.8Chapter 2.2.2 --- Port-to-port isolation --- p.8Chapter 2.2.3 --- Noise figure --- p.9Chapter 2.2.4 --- 1-dB compression point (P1dB) --- p.11Chapter 2.2.5 --- 2nd order intercept point (IP2) --- p.11Chapter 2.2.6 --- 3rd order intercept point (IP3) --- p.12Chapter 2.2.7 --- Blocking dynamic range (BDR) --- p.12Chapter 2.2.8 --- Spurious free dynamic range (SFDR) --- p.12Chapter 2.2 --- Review of mixer architectures --- p.13Chapter 2.2.1 --- Diode mixer --- p.13Chapter 2.2.2 --- Dual-gate mxer --- p.14Chapter 2.2.3 --- Singly balanced mixer --- p.15Chapter 2.2.4 --- Doubly balanced dual-gate mixer --- p.16Chapter 2.2.5 --- Gilbert cell mixer --- p.18Chapter Chapter 3 --- CMOS Doubly Balanced Dual-Gate Mixer Design --- p.20Chapter 3.1 --- Design and Analysis --- p.20Chapter 3.1.1 --- Principle of operation --- p.20Chapter 3.1.2 --- Doubly balanced dual-gate mixer --- p.23Chapter 3.1.3 --- Common source output buffer --- p.25Chapter 3.1.4 --- Design example and simulation results --- p.26Chapter 3.2 --- IC Layout --- p.29Chapter 3.2.1 --- Multi-fingers transistor --- p.29Chapter 3.2.2 --- Matched transistor --- p.31Chapter 3.2.3 --- Match resistor --- p.32Chapter 3.2.4 --- Layout of CMOS doubly balanced dual-gate mixer --- p.33Chapter Chapter 4 --- Review of Mixer Linearization Techniques --- p.34Chapter 4.1 --- Source degeneration --- p.34Chapter 4.2 --- Feed-forward system --- p.36Chapter 4.3 --- Predistortion --- p.38Chapter 4.4 --- Difference-frequency (low-frequency) injection technique --- p.41Chapter Chapter 5 --- Mixer Linearization 一 Low Frequency Signal Injection --- p.44Chapter 5.1 --- Mixer's linearity --- p.44Chapter 5.2 --- Low-frequency signal injection method --- p.46Chapter 5.2.1 --- Single-injection scheme --- p.49Chapter 5.2.2 --- Dual-injection scheme --- p.50Chapter 5.2.3 --- Effect of gain error --- p.51Chapter 5.2.4 --- Bandwidth lim itation --- p.52Chapter Chapter 6 --- Experiments and Results --- p.55Chapter 6.1 --- CMOS doubly balanced dual-gate mixer --- p.55Chapter 6.1.1 --- Conversion gain --- p.56Chapter 6.1.2 --- Port-to-port isolation --- p.57Chapter 6.1.3 --- No ise figure --- p.60Chapter 6.1.4 --- 1-dB compression point --- p.61Chapter 6.1.5 --- 3rd order intercept point --- p.62Chapter 6.2 --- Low-frequency signal injection method --- p.63Chapter 6.2.1 --- Measurement result: single-injection scheme --- p.64Chapter 6.2.2 --- Measurement result: dual-injection scheme --- p.66Chapter Chapter 7 --- Conclusions and Recommendations for Future Work --- p.68Chapter 7.1 --- Conclusions --- p.68Chapter 7.2 --- Recommendations for future work --- p.69Appendix --- p.70Chapter A1 --- CMOS technology --- p.70Chapter A1.1 --- MOSFET structure --- p.70Chapter A1.2 --- CMOS n-well process --- p.71Chapter A1.3 --- MOSFET device modeling --- p.74Chapter A1.4 --- Channel length modulation --- p.78Chapter A1.5 --- Body effect --- p.78Chapter A2 --- Mixer's nonlinearity analysis --- p.79Chapter A2.1 --- First-order effect --- p.79Chapter A2.2 --- Second-order effect --- p.80Chapter A2.3 --- Third-order effect --- p.81Chapter A2.4 --- Nonlinear IF spectrum --- p.82Chapter A3 --- Artificial IMD3 produced by low-frequency signal injection --- p.83Author's Publication List --- p.85References --- p.8

Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin

Low-Power Wake-Up Receivers

The Internet of Things (IoT) is leading the world to the Internet of Everything (IoE), where things, people, intelligent machines, data and processes will be connected together. The key to enter the era of the IoE lies in enormous sensor nodes being deployed in the massively expanding wireless sensor networks (WSNs). By the year of 2025, more than 42 billion IoT devices will be connected to the Internet. While the future IoE will bring priceless advantages for the life of mankind, one challenge limiting the nowadays IoT from further development is the ongoing power demand with the dramatically growing number of the wireless sensor nodes. To address the power consumption issue, this dissertation is motivated to investigate low-power wake-up receivers (WuRXs) which will significantly enhance the sustainability of the WSNs and the environmental awareness of the IoT. Two proof-of-concept low-power WuRXs with focuses on two different application scenarios have been proposed. The first WuRX, implemented in a cost-effective 180-nm CMOS semiconductor technology, operates at 401−406-MHz band. It is a good candidate for application scenarios, where both a high sensitivity and an ultra-low power consumption are in demand. Concrete use cases are, for instance, medical implantable applications or long-range communications in rural areas. This WuRX does not rely on a further assisting semiconductor technology, such as MEMS which is widely used in state-of-the-art WuRXs operating at similar frequencies. Thus, this WuRX is a promising solution to low-power low-cost IoT. The second WuRX, implemented in a 45-nm RFSOI CMOS technology, was researched for short-range communication applications, where high-density conventional IoT devices should be installed. By investigation of the WuRX for operation at higher frequency band from 5.5 GHz to 7.5 GHz, the nowadays ever more over-traffic issues that arise at low frequency bands such as 2.4 GHz can be substantially addressed. A systematic, analytical research route has been carried out in realization of the proposed WuRXs. The thesis begins with a thorough study of state-of-the-art WuRX architectures. By examining pros and cons of these architectures, two novel architectures are proposed for the WuRXs in accordance with their specific use cases. Thereon, key WuRX parameters are systematically analyzed and optimized; the performance of relevant circuits is modeled and simulated extensively. The knowledge gained through these investigations builds up a solid theoretical basis for the ongoing WuRX designs. Thereafter, the two WuRXs have been analytically researched, developed and optimized to achieve their highest performance. Proof-of-concept circuits for both the WuRXs have been fabricated and comprehensively characterized under laboratory conditions. Finally, measurement results have verified the feasibility of the design concept and the feasibility of both the WuRXs