Design and implementation of an ETSI-SDR OFDM transmitter with power amplifier linearizer

Satellite radio has attained great popularity because of its wide range of geographical coverage and high signal quality as compared to the terrestrial broadcasts. Most Satellite Digital Radio (SDR) based systems favor multi-carrier transmission schemes, especially, orthogonal frequency division multiplexing (OFDM) transmission because of high data transfer rate and spectral efficiency. It is a challenging task to find a suitable platform that supports fast data rates and superior processing capabilities required for the development and deployment of the new SDR standards. Field programmable gate array (FPGA) devices have the potential to become suitable development platform for such standards. Another challenging factor in SDR systems is the distortion of variable envelope signals used in OFDM transmission by the nonlinear RF power amplifiers (PA) used in the base station transmitters. An attractive option is to use a linearizer that would compensate for the nonlinear effects of the PA. In this research, an OFDM transmitter, according to European Telecommunications Standard Institute (ETSI) SDR Technical Specifications 2007-2008, was designed and implemented on a low-cost Xilinx FPGA platform. A weakly nonlinear PA, operating in the L-band SDR frequency (1.450-1.490GHz), was used for signal transmission. An FPGA-based, low-cost, adaptive linearizer was designed and implemented based on the digital predistortion (DPD) reference design from Xilinx, to correct the distortion effects of the PA on the transmitted signal

Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies

Modelling and performance analysis of multigigabit serial interconnects using real number based analog verification methods

The increasing importance of multigigabit transceiver circuits in modern chip design calls for new methods of analyzing and integrating these challenging building blocks. This work presents a design and analysis framework basend on the SystemVerilog real number modeling ansatz. It further extends the simulation possibilities thus obtained by introducing additional higher level numeric modelling and evaluation methods to support multigigabit statistical link budgeting procedures based on the Peak Distortion Algorithm

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

GSI Scientific Report 2009 [GSI Report 2010-1]

Displacement design response spectrum is an essential component for the currently-developing displacement-based seismic design and assessment procedures. This paper proposes a new and simple method for constructing displacement design response spectra on soft soil sites. The method takes into account modifications of the seismic waves by the soil layers, giving due considerations to factors such as the level of bedrock shaking, material non-linearity, seismic impedance contrast at the interface between soil and bedrock, and plasticity of the soil layers. The model is particularly suited to applications in regions with a paucity of recorded strong ground motion data, from which empirical models cannot be reliably developed