A 250-ps integrated ultra-wideband timed array beamforming receiver in 0.18 um CMOS

This paper presents a 4-channel ultra-wideband (UWB) timed array beamforming receiver designed in a standard 0.18-um CMOS technology. The proposed timed array receiver achieves a maximum delay of 250 ps at the maximum beam steering angle of +/-42o with 10.5o (8 steps) steering resolution and 2-cm antenna spacing. Each receiver channel provides gains ranging from 3.6 to -35 dB and less than 8% delay variation for all delay settings over a 3.1-10.6-GHz frequency range, while consuming a maximum of 58 mW power from a 1.8-V supply. The average -1-dB compression point P1dB is -9.9 dBm. The proposed architecture is modeled and simulated by using Virtuoso Cadence.This work has been partially supported by the Spanish Ministerio de Ciencia, Innovacion y Universidades (MICINN)- ´ Agencia Estatal de Investigacion (AEI) and the European ´ Regional Development Funds (FEDER), by project PGC2018- 098946-B-I00.Peer ReviewedPostprint (author's final draft

Timed array antenna system : application to wideband and ultra-wideband beamforming receivers

Antenna array systems have a broad range of applications in radio frequency (RF) and ultra-wideband (UWB) communications to receive/transmit electromagnetic waves from/to the sky. They can enhance the amplitude of the input signals, steer beams electronically, and reject interferences thanks to beamforming technique. In an antenna array beamforming system, delay cells with the tunable capability of delay amount compensate the relative delay of signals received by antennas. In fact, each antenna almost acts individually depending upon time delaying effects on the input signals. As a result, the delay cells are the basic elements of the beamforming systems. For this purpose, novel active true time delay (TTD) cells suitable for RF antenna arrays have been presented in this thesis. These active delay cells are based on 1st- and 2nd-order all-pass filters (APFs) and achieve quite a flat gain and delay within up to 10-GHz frequency range. Various techniques such as phase linearity and delay tunability have been accomplished to improve the design and performance. The 1st-order APF has been designed for a frequency range of 5 GHz, showing desirable frequency responses and linearity which is comparable with the state-of-the-art. This 1st-order APF is able to convert into a 2nd-order APF via adding a grounded capacitor. A compact 2nd-order APF using an active inductor has been also designed and simulated for frequencies up to 10 GHz. The active inductor has been utilized to tune the amount of delay and to reduce the on-chip size of the filter. In order to validate the performance of the delay cells, two UWB four-channel timed array beamforming receivers realized by the active TTD cells have been proposed. Each antenna channel exploits digitally controllable gain and delay on the input signal and demonstrates desirable gain and delay resolutions. The beamforming receivers have been designed for different UWB applications depending on their operating frequency ranges (that is, 3-5 and 3.1-10.6 GHz), and thus they have different system requirements and specifications. All the circuits and topologies presented in this dissertation have been designed in standard 180-nm CMOS technologies, featuring a unity gain frequency ( ft) up to 60 GHz.Els sistemes matricials d’antenes tenen una àmplia gamma d’aplicacions en radiofreqüència (RF) i comunicacions de banda ultraampla (UWB) per rebre i transmetre ones electromagnètics. Poden millorar l’amplitud dels senyals d’entrada rebuts, dirigir els feixos electrònicament i rebutjar les interferències gràcies a la tècnica de formació de feixos (beamforming). En un sistema beamforming de matriu d’antenes, les cèl·lules de retard amb capacitat ajustable del retard, compensen aquest retard relatiu dels senyals rebuts per les diferents antenes. De fet, cada antena gairebé actua individualment depenent dels efectes de retard de temps sobre el senyals d’entrada. Com a resultat, les cel·les de retard són els elements bàsics en el disseny dels actuals sistemes beamforming. Amb aquest propòsit, en aquesta tesi es presenten noves cèl·lules actives de retard en temps real (TTD, true time delay) adequades per a matrius d’antenes de RF. Aquestes cèl·lules de retard actives es basen en cèl·lules de primer i segon ordre passa-tot (APF), i aconsegueixen un guany i un retard força plans, en el rang de freqüència de fins a 10 GHz. Diverses tècniques com ara la linealitat de fase i la sintonització del retard s’han aconseguit per millorar el disseny i el rendiment. La cèl·lula APF de primer ordre s’ha dissenyat per a un rang de freqüències de fins a 5 GHz, mostrant unes respostes freqüencials i linealitat que són comparables amb l’estat de l’art actual. Aquestes cèl·lules APF de primer ordre es poden convertir en un APF de segon ordre afegint un condensador més connectat a massa. També s’ha dissenyat un APF compacte de segon ordre que utilitza una emulació d’inductor actiu per a freqüències de treball de fins a 10 GHz. S’ha utilitzat l'inductor actiu per ajustar la quantitat de retard introduït i reduir les dimensions del filtre al xip. Per validar les prestacions de les cel·les de retard propostes, s’han proposat dos receptors beamforming basats en matrius d’antenes de 4 canals, realitzats por cèl·lules TTD actives. Cada canal d’antena aprofita el guany i el retard controlables digitalment aplicats al senyal d’entrada, i demostra resolucions de guany i retard desitjables. Els receptors beamforming s’han dissenyat per a diferents aplicacions UWB segons els seus rangs de freqüències de funcionament (en aquest cas, 3-5 i 3,1-10,6 GHz) i, per tant, tenen diferents requisits i especificacions de disseny del sistema. Tots els circuits i topologies presentats en aquesta tesi s’han dissenyat en tecnologies CMOS estàndards de 180 nm, amb una freqüència de guany unitari (ft) de fins a 60 GHz.Postprint (published version

High-Speed Wide-Field Time-Correlated Single-Photon Counting Fluorescence Lifetime Imaging Microscopy

Fluorescence microscopy is a powerful imaging technique used in the biological sciences to identify labeled components of a sample with specificity. This is usually accomplished through labeling with fluorescent dyes, isolating these dyes by their spectral signatures with optical filters, and recording the intensity of the fluorescent response. Although these techniques are widely used, fluorescence intensity images can be negatively affected by a variety of factors that impact the fluorescence intensity. Fluorescence lifetime imaging microscopy (FLIM) is an imaging technique that is relatively immune to intensity fluctuations and also provides the unique ability to directly monitor the microenvironment surrounding a fluorophore. Despite the benefits associated with FLIM, the applications to which it is applied are fairly limited due to long image acquisition times and high cost of traditional hardware. Recent advances in complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) have enabled the design of low-cost imaging arrays that are capable of recording lifetime images with acquisition times greater than one order of magnitude faster than existing systems. However, these SPAD arrays have yet to realize the full potential of the technology due to limitations in their ability to handle the vast amount of data generated during the commonly used time-correlated single-photon counting (TCSPC) lifetime imaging technique. This thesis presents the design, implementation, characterization, and demonstration of a high speed FLIM imaging system. The components of this design include a CMOS imager chip in a standard 0.13 μm technology containing a custom CMOS SPAD, a 64-by-64 array of these SPADs, pixel control circuitry, independent time-to-digital converters (TDCs), a FLIM specific datapath, and high bandwidth output buffers. In addition to the CMOS imaging array, a complete system was designed and implemented using a printed circuit board (PCB) for capturing data from the imager, creating histograms for the photon arrival data using field-programmable gate arrays, and transferring the data to a computer using a cabled PCIe interface. Finally, software is used to communicate between the imaging system and a computer.The dark count rate of the SPAD was measured to be only 231 Hz at room temperature while maintaining a photon detection probability of up to 30\%. TDCs included on the array have a 62.5 ps resolution and a 64 ns range, which is suitable for measuring the lifetime of most biological fluorophores. Additionally, the on-chip datapath was designed to handle continuous data transfers at rates capable of supporting TCSPC-based lifetime imaging at 100 frames per second. The system level implementation also provides sufficient data throughput for transferring up to 750 frames per second from the imaging system to a computer. The lifetime imaging system was characterized using standard techniques for evaluating SPAD performance and an electrical delay signal for measuring the TDC performance. This thesis concludes with a demonstration of TCSPC-FLIM imaging at 100 frames per second -- the fastest 64-by-64 TCSPC FLIM that has been demonstrated. This system overcomes some of the limitations of existing FLIM systems and has the potential to enable new application domains in dynamic FLIM imaging

Circuit Design Techniques For Wideband Phased Arrays

University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM$_{T}$ values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth

High Frequency Devices and Circuit Modules for Biochemical Microsystems

This dissertation investigates high frequency devices and circuit modules for biochemical microsystems. These modules are designed towards replacing external bulky laboratory instruments and integrating with biochemical microsystems to generate and analyze signals in frequency and time domain. The first is a charge pump circuit with modified triple well diodes, which is used as an on-chip power supply. The second is an on-chip pulse generation circuit to generate high voltage short pulses. It includes a pulse-forming-line (PFL) based pulse generation circuit, a Marx generator and a Blumlein generator. The third is a six-port circuit based on four quadrature hybrids with 2.0~6.0 GHz operating frequency tuning range for analyzing signals in frequency domain on-chip. The fourth is a high-speed sample-and-hold circuit (SHC) with a 13.3 Gs/s sampling rate and ~11.5 GHz input bandwidth for analyzing signals in time domain on-chip. The fifth is a novel electron spin resonance (ESR) spectroscopy with high-sensitivity and wide frequency tuning range

The Design of Low Power Ultra-Wideband Transceiver

Ph.DDOCTOR OF PHILOSOPH

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise

SiGe/CMOS Millimeter-Wave Integrated Circuits and Wafer-Scale Packaging for Phased Array Systems.

Phased array systems have been used to achieve electronic beam control and fast beam scanning. In the RF-phase shifting architecture, T/R modules are required for each antenna element, and have been traditionally developed using GaAs or InP technology. This thesis demonstrates that Ka-band (35 GHz) T/R modules can also be developed using the SiGe BiCMOS technology. The designed circuit blocks include a low noise amplifier, a 4-bit phase shifter, a variable gain amplifier/attenuator, and SPDT switches. The Ka-band phase shifters are designed based on CMOS switch and miniature low-pass networks for a single-ended and differential applications, and result in 3-degree rms phase error at 35 GHz. The SiGe LNA results in a peak gain of 24 dB and a noise figure of 2.9-3.1 dB with 11 mW power consumption. The CMOS variablestep attenuator has 12-dB attenuation range (1 dB step) with very low loss and phase imbalance at 10-50 GHz. A variable gain LNA is also demonstrated at 30-40 GHz for the differential phased array receiver, and has 20-dB gain and <1-degree rms phase imbalance between the 8 different gain states and 10 dB gain control. All of these circuits show state-of-the-art performance, and the phase shifter, distributed attenuator and VGA are also first-time demonstrations at Ka-band frequencies. These circuit blocks were used in a miniature SiGe/CMOS Ka-band T/R module with a dimension of 0.93x1.33mm2, and a measured performance of 19 dB receive gain, 4-5 dB NF, 9 dB transmit gain and +5.5 dBm output P1dB. The T/R module also has 4-bit phase control and 10 dB gain control in both the transmit and receive modes. To our knowledge, this is the first demonstration of a Ka-band SiGe/CMOS T/R module to-date. Finally, a DC-110 GHz Si wafer-scale packaging technique has been developed using thermo-compression bonding and is suitable for Ka-band and even W-band T/R modules. The package transition has an insertion loss of 0.1-0.26 dB at 30-110 GHz, and the package resonances and leakage were drastically reduced by grounding the sealing ring. This is the first demonstration of a wideband resonance-free (DC-110 GHz) package using silicon technology.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58380/1/bmin_1.pd