1,477 research outputs found
Attosecond Precision Multi-km Laser-Microwave Network
Synchronous laser-microwave networks delivering attosecond timing precision
are highly desirable in many advanced applications, such as geodesy,
very-long-baseline interferometry, high-precision navigation and
multi-telescope arrays. In particular, rapidly expanding photon science
facilities like X-ray free-electron lasers and intense laser beamlines require
system-wide attosecond-level synchronization of dozens of optical and microwave
signals up to kilometer distances. Once equipped with such precision, these
facilities will initiate radically new science by shedding light on molecular
and atomic processes happening on the attosecond timescale, such as
intramolecular charge transfer, Auger processes and their impact on X-ray
imaging. Here, we present for the first time a complete synchronous
laser-microwave network with attosecond precision, which is achieved through
new metrological devices and careful balancing of fiber nonlinearities and
fundamental noise contributions. We demonstrate timing stabilization of a
4.7-km fiber network and remote optical-optical synchronization across a 3.5-km
fiber link with an overall timing jitter of 580 and 680 attoseconds RMS,
respectively, for over 40 hours. Ultimately we realize a complete
laser-microwave network with 950-attosecond timing jitter for 18 hours. This
work can enable next-generation attosecond photon-science facilities to
revolutionize many research fields from structural biology to material science
and chemistry to fundamental physics.Comment: 42 pages, 13 figure
Numerical investigation of a feed-forward linewidth reduction scheme using a mode-locked laser model of reduced complexity
We provide numerical verification of a feed-forward, heterodyne-based phase noise reduction scheme using
single-sideband modulation that obviates the need for optical filtering at the output. The main benefit of a
feed-forward heterodyne linewidth reduction scheme is the simultaneous reduction of the linewidth of all modes
of a mode-locked laser (MLL) to that of a narrow-linewidth single-wavelength laser. At the heart of our simulator
is an MLL model of reduced complexity. Importantly, the main issue being treated is the jitter of MLLs and we
show how to create numerical waveforms that mimic the random-walk nature of timing jitter of pulses from
MLLs. Thus, the model does not need to solve stochastic differential equations that describe the MLL dynamics,
and the model calculates self-consistently the line-broadening of the modes of the MLL and shows good agreement with both the optical linewidth and jitter. The linewidth broadening of the MLL modes are calculated after
the phase noise reduction scheme and we confirm that the phase noise contribution from the timing jitter still
remains. Finally, we use the MLL model and phase noise reduction simulator within an optical communications
system simulator and show that the phase noise reduction technique could enable MLLs as optical carriers for
higher-order modulation formats, such as 16-state and 64-state quadrature amplitude modulation
Versatile Digital GHz Phase Lock for External Cavity Diode Lasers
We present a versatile, inexpensive and simple optical phase lock for
applications in atomic physics experiments. Thanks to all-digital phase
detection and implementation of beat frequency pre-scaling, the apparatus
requires no microwave-range reference input, and permits phase locking at
frequency differences ranging from sub-MHz to 7 GHz (and with minor extension,
to 12 GHz). The locking range thus covers ground state hyperfine splittings of
all alkali metals, which makes this system a universal tool for many
experiments on coherent interaction between light and atoms.Comment: 4.5 pages, 5 figures v3: fixed error in schematic: R10 connects to
other end of C
๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ๋ฅผ ์ํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ๋ฅผ ๊ธฐ๋ฐ์ผ๋ก ํ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links.
To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power.
As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.๋ณธ ๋
ผ๋ฌธ์ ํ๋ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ๊ด์ฌ๋๋ ์ฃผ์ํ ๋ฌธ์ ๋ค์ ๋ํ์ฌ ๊ธฐ์ ํ๋ค. ์ค์๋, ๋ค์ค ํ์ค ๊ตฌ์กฐ๋ค์ด ์ฑํ๋๊ณ ์๋ ์ถ์ธ์ ๋ฐ๋ผ, ๊ธฐ์กด์ ํด๋ผํน ๋ฐฉ๋ฒ์ ๋ฎ์ ๋น์ฉ์ ๊ตฌํ์ ๊ด์ ์์ ์๋ก์ด ํ์ ์ ํ์๋ก ํ๋ค. LC ๊ณต์ง๊ธฐ๋ฅผ ๋์ ํ์ฌ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๋ฅผ ์ฌ์ฉํ ์ฃผํ์ ํฉ์ฑ์ ๋ํ์ฌ ์์๋ณด๊ณ , ์ด์ ๋ฐ์ํ๋ ๋๊ฐ์ง ์ฃผ์ ๋ฌธ์ ์ ๊ณผ ๊ฐ๊ฐ์ ๋ํ ํด๊ฒฐ ๋ฐฉ์์ ํ์ํ๋ค. ๊ฐ ์ ์ ๋ฐฉ๋ฒ์ ํ๋กํ ํ์
์นฉ์ ํตํด ๊ทธ ํจ์ฉ์ฑ์ ๊ฒ์ฆํ๊ณ , ์ด์ด์ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๊ฐ ๋ฏธ๋์ ๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ์ฌ์ฉ๋ ๊ฐ๋ฅ์ฑ์ ๋ํด ๊ฒํ ํ๋ค.
์ฒซ๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ์ฃผํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ํ๋ฆฌ์ปค ์ก์์ ์ํ์ํค๊ธฐ ์ํด ๊ธฐ์ค ์ ํธ๋ฅผ ๋ฐฐ์ํํ์ฌ ๋ท๋จ์ ์์ ๊ณ ์ ๋ฃจํ์ ๋์ญํญ์ ํจ๊ณผ์ ์ผ๋ก ๊ทน๋ํ ์ํค๋ ํ๋ก ๊ธฐ์ ์ ์ ์ํ๋ค. ๋ณธ ๊ธฐ์ ์ ์งํฐ๋ฅผ ๋์ ์ํค์ง ์์ผ๋ฉฐ ๋ฐ๋ผ์ ๊นจ๋ํ ์ค๊ฐ ์ฃผํ์ ํด๋ฝ์ ์์ฑ์์ผ ์์ ๊ณ ์ ๋ฃจํ์ ํจ๊ป ๋์ ์ฑ๋ฅ์ ๊ณ ์ฃผํ ํด๋ฝ์ ํฉ์ฑํ๋ค. ๊ธฐ์ค ์ ํธ๋ฅผ ์ฑ๊ณต์ ์ผ๋ก ๋ฐฐ์ํํ๊ธฐ ์ํ ํ์ด๋ฐ ์กฐ๊ฑด๋ค์ ๋จผ์ ๋ถ์ํ์ฌ ํ์ด๋ฐ ์ค๋ฅ๋ฅผ ์ ๊ฑฐํ๊ธฐ ์ํ ๋ฐฉ๋ฒ๋ก ์ ํ์
ํ๋ค. ๊ฐ ๊ต์ ์ค๋์ ์ฐ์ญ์ ํ๋ฅ ์ ๊ธฐ๋ฐ์ผ๋กํ LMS ์๊ณ ๋ฆฌ์ฆ์ ํตํด ๊ฐฑ์ ๋๋๋ก ์ค๊ณ๋๋ค. ๊ต์ ์ ํ์ํ ์๊ฐ์ ์ต์ํ ํ๊ธฐ ์ํ์ฌ, ๊ฐ ๊ต์ ์ด๋์ ํ์ด๋ฐ ์ค๋ฅ ๊ทผ์๋ค์ ํฌ๊ธฐ๋ฅผ ๊ท๋ฉ์ ์ผ๋ก ์ถ๋ก ํ ๊ฐ์ ๋ฐํ์ผ๋ก ์ง์์ ์ผ๋ก ์ ์ด๋๋ค. 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋ ํ๋กํ ํ์
์นฉ์ ์ธก์ ์ ํตํด ์ ์์, ๊ณ ์ฃผํ ํด๋ฝ์ ๋น ๋ฅธ ๊ต์ ์๊ฐ์์ ํฉ์ฑํด ๋์ ํ์ธํ์๋ค. ์ด๋ 177/223 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8/16 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค.
๋๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ์ ์ ๋
ธ์ด์ฆ ์์กด์ฑ์ ์ํ์ํค๋ ๊ธฐ์ ์ด ํฌํจ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ๊ฐ ์ค๊ณ๋์๋ค. ์ด๋ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ์ ์ ํค๋๋ฃธ์ ๋ณด์กดํจ์ผ๋ก์ ๊ณ ์ฃผํ ๋ฐ์ง์ ๊ฐ๋ฅํ๊ฒ ํ๋ค. ๋์๊ฐ, ์ ์ ๋
ธ์ด์ฆ ๊ฐ์ ์ฑ๋ฅ์ ๊ณต์ , ์ ์, ์จ๋ ๋ณ๋์ ๋ํ์ฌ ๋ฏผ๊ฐํ์ง ์์ผ๋ฉฐ, ๋ฐ๋ผ์ ์ถ๊ฐ์ ์ธ ๊ต์ ํ๋ก๋ฅผ ํ์๋ก ํ์ง ์๋๋ค. ๋ง์ง๋ง์ผ๋ก, ์์ ๋
ธ์ด์ฆ์ ๋ํ ํฌ๊ด์ ๋ถ์๊ณผ ํ๋ก ์ต์ ํ๋ฅผ ํตํ์ฌ ์ฃผํ์ ํฉ์ฑ๊ธฐ์ ์ ์ก์ ์ถ๋ ฅ์ ๋ฐฉํดํ์ง ์๋ ๋ฐฉ๋ฒ์ ๊ณ ์ํ์๋ค. ํด๋น ํ๋กํ ํ์
์นฉ์ 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋์์ผ๋ฉฐ, ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์ง ์์ ์ํ์์ 289 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค. ๋ํ, 20 mVrms์ ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์์ ๋์ ์ ๋๋๋ ์งํฐ์ ์์ -23.8 dB ๋งํผ ์ค์ด๋ ๊ฒ์ ํ์ธํ์๋ค.1 Introduction 1
1.1 Motivation 3
1.1.1 Clocking in High-Speed Serial Links 4
1.1.2 Multi-Phase, High-Frequency Clock Conversion 8
1.2 Dissertation Objectives 10
2 RO-Based High-Frequency Synthesis 12
2.1 Phase-Locked Loop Fundamentals 12
2.2 Toward All-Digital Regime 15
2.3 RO Design Challenges 21
2.3.1 Oscillator Phase Noise 21
2.3.2 Challenge 1: High Flicker Noise 23
2.3.3 Challenge 2: High Supply Noise Sensitivity 26
3 Filtering RO Noise 28
3.1 Introduction 28
3.2 Proposed Reference Octupler 34
3.2.1 Delay Constraint 34
3.2.2 Phase Error Calibration 38
3.2.3 Circuit Implementation 51
3.3 IL-ADPLL Implementation 55
3.4 Measurement Results 59
3.5 Summary 63
4 RO Supply Noise Compensation 69
4.1 Introduction 69
4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72
4.2.1 Circuit Implementation 73
4.2.2 Frequency-Domain Analysis 76
4.2.3 Circuit Optimization 81
4.3 ADPLL Implementation 87
4.4 Measurement Results 90
4.5 Summary 98
5 Conclusions 99
A Notes on the 8REF 102
B Notes on the ACSC 105๋ฐ
Exceeding octave tunable Terahertz waves with zepto-second level timing noise
Spectral purity of any millimeter wave (mmW) source is of the utmost interest
in low-noise applications. Optical synthesis via photomixing is an attractive
source for such mmWs, which usually involves expensive spectrally pure lasers
with narrow linewidths approaching monochromaticity due to their inherent
fabrication costs or specifications. Here, we report an alternative option for
enhancing the spectral purity of inexpensive semiconductor diode lasers via a
self-injection locking technique through corresponding Stokes waves from a
fiber Brillouin cavity exhibiting greatly improved phase noise levels and large
wavelength tunability of ~1.8 nm. We implement a system with two self-injected
diode lasers on a common Brillouin cavity aimed at difference frequency
generation in the mmW and THz region. We generate tunable sub-mmW (0.3 and 0.5
THz) waves by beating the self-injected two wavelength Stokes light on a
uni-travelling carrier photodiode and characterize the noise performance. The
sub-mmW features miniscule timing noise levels in the zepto-second (zs.Hz^-0.5)
scale outperforming the state of the art dissipative Kerr soliton based
micro-resonator setups while offering broader frequency tunability. These
results suggest a viable inexpensive alternative for mmW sources aimed at
low-noise applications featuring lab-scale footprints and rack-mounted
portability while paving the way for chip-scale photonic integration.Comment: 31 page
A Bang-Bang All-Digital PLL for Frequency Synthesis
abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201
Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems
Ultraยฌwide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system.
A mixerยฌbased frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phaseยฌlocked loop (PLL)ยฌbased synthesizers. Harmonic cancelaยฌtion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5ยฌGHz CSDยฌQVCO in 0.18 ยตm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ยฌ120 dBc at 3 MHz o๏ฌset. Compared with existing phase shift LC QVCOs, the proposed CSDยฌQVCO presents better phase noise and power e๏ฌciency.
Finally, a novel injection locking frequency divider (ILFD) is presented. Imยฌplemented with three stages in 0.18 ยตm CMOS technology, the ILFD draws 3ยฌmA current from a 1.8ยฌV power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range
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