Fully differential implementation of a delta-sigma modulator based on the pseudo-pseudo differential technique

Flicker noise and distortion are the main limitations in biomedical applications, especially for Switched Capacitor implementations, where the flicker noise is folded into the signal band. To remove the flicker noise and increase the linearity, the Pseudo-Pseudo Differential (P2D) technique has been proposed, where a single-ended signal is processed in a differential way. This paper presents the first silicon implementation of a second order Comparator-Based Switched-Capacitor (CBSC) delta-sigma modulator based on a variation of the P2D technique. Experimental results in a standard 180 nm CMOS technology show an improvement of 10 dB in the Peak SNDR, 5 dB in the DR, and 9 dB in the SFDR over its pseudo differential counterpart, which is the preferred differential implementation for CBSC circuits. Moreover, it is achieved with a reduction in the power consumption

A 1W 8-ratio switched-capacitor boost power converter in 140nm CMOS with 94.5% efficiency, 0.5mm thickness and 8.1mm2 PCB area

This paper presents a boost switched-capacitor power converter (SCPC) in 140nm CMOS converting a wide input voltage range (2.6V to 4.2V) to an output voltage of 5V at 1W output power. It achieves the highest applicable number of conversion ratios with the lowest number of floating capacitors to date. With 8 conversion ratios and only 4 small floating capacitors, a high peak efficiency of 94.5%, a very small PCB area of 8.1mm2, and a low thickness of 0.5mm are achieved