A 216–256 GHz fully differential frequency multiplier-by-8 chain with 0 dBm output power

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.This work presents a fully differential wideband and low power 240 GHz multiplier-by-8 chain, manufactured in IHP's 130 nm SiGe:C BiCMOS technology with fT/fmax = 300/500 GHz. A single ended 30 GHz input signal is multiplied by 8 using Gilbert cell-based quadrupler and doubler, and then amplified with a wideband differential 3-stage cascode amplifier. To achieve wide bandwidth and optimize for power consumption, the power budget has been designed in order to operate the frequency multipliers and the output amplifier in saturation. With this architecture the presented circuit achieves a 3 dB bandwidth of 40 GHz, meaning a relative 3 dB bandwidth of 17%, and a peak saturated output power of 0 dBm. Harmonic rejections better than 25 dB were measured for the 5th, 6th, and 7th harmonics. It dissipates 255 mW from 3 V supply which results in drain efficiency of 0.4%, while occupying 1.2 mm2. With these characteristics the presented circuit suits very well as a frequency multiplier chain for driving balanced mixers in 240 GHz transceivers for radar, communication, and sensing applications.DFG, 255715243, SPP 1857: Elektromagnetische Sensoren für Life Sciences (ESSENCE

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

Millimeter-Wave and Terahertz Transceivers in SiGe BiCMOS Technologies

This invited paper reviews the progress of silicon–germanium (SiGe) bipolar-complementary metal–oxide–semiconductor (BiCMOS) technology-based integrated circuits (ICs) during the last two decades. Focus is set on various transceiver (TRX) realizations in the millimeter-wave range from 60 GHz and at terahertz (THz) frequencies above 300 GHz. This article discusses the development of SiGe technologies and ICs with the latter focusing on the commercially most important applications of radar and beyond 5G wireless communications. A variety of examples ranging from 77-GHz automotive radar to THz sensing as well as the beginnings of 60-GHz wireless communication up to THz chipsets for 100-Gb/s data transmission are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of SiGe TRX performance

ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER

This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources. RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands. Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system. A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured. A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network

準ミリ波・ミリ波領域における低位相雑音電圧制御発振器のLC共振器に関する研究

2017岡山県立大学大学

Quadrature Frequency Synthesis for Wideband Wireless Transceivers

University of Minnesota Ph.D. dissertation. May 2014. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xi, 112 pages.In this thesis, three different techniques pertinent to quadrature LO generation in high data rate and wideband RF transceivers are presented. Prototype designs are made to verify the performance of the proposed techniques, in three different technologies: IBM 130nm CMOS process, TSMC 65nm CMOS process and IBM 32nm SOI process. The three prototype designs also cover three different frequency bands, ranging from 5GHz to 74GHz. First, an LO generation scheme for a 21 GHz center-frequency, 4-GHz instantaneous bandwidth channelized receiver is presented. A single 1.33 GHz reference source is used to simultaneously generate 20 GHz and 22 GHz LOs with quadrature outputs. Injection locking is used instead of conventional PLL techniques allowing low-power quadrature generation. A harmonic-rich signal, containing both even and odd harmonics of the input reference signal, is generated using a digital pulse slimmer. Two ILO chains are used to lock on to the 10th and 11th harmonics of the reference signal generating the 20 GHz and the 22 GHz quadrature LOs respectively. The prototype design is implemented in IBM's 130 nm CMOS process, draws 110 mA from a 1.2 V supply and occupies an active area of 1.8 square-mm. Next, a wide-tuning range QVCO with a novel complimentary-coupling technique is presented. By using PMOS transistors for coupling two VCOs with NMOS gm-cells, it is shown that significant phase-noise improvement (7-9 dB) can be achieved over the traditional NMOS coupling. This breaks the trade-off between quadrature accuracy and phase-noise, allowing reasonable accuracy without a significant phase-noise hit. The proposed technique is frequency-insensitive, allowing robust coupling over a wide tuning range. A prototype design is done in TSMC 65nm process, with 4-bits of discrete tuning spanning the frequency range 4.6-7.8 GHz (52% FTR) while achieving a minimum FOM of 181.4dBc/Hz and a minimum FOMT of 196dBc/Hz. Finally, a wide tuning-range millimeter wave QVCO is presented that employs a modified transformer-based super-harmonic coupling technique. Using the proposed technique, together with custom-designed inductors and metal capacitors, a prototype is designed in IBM 32nm SOI technology with 6-bits of discrete tuning using switched capacitors. Full EM-extracted simulations show a tuning range of 53.84GHz to 73.59GHz, with an FOM of 173 dBc/Hz and an FOMT of 183 dBc/Hz. With 19.75GHz of tuning range around a 63.7GHz center frequency, the simulated FTR is 31%, surpassing all similar designs in the same band. A slight modification in the tank inductors would enable the QVCO to be employed in multiple mm-Wave bands (57-66 GHz communication band, 71-76 GHz E-band, and 76-77 GHz radar band)

Terahertz Technology and Its Applications

The Terahertz frequency range (0.1 – 10)THz has demonstrated to provide many opportunities in prominent research fields such as high-speed communications, biomedicine, sensing, and imaging. This spectral range, lying between electronics and photonics, has been historically known as “terahertz gap” because of the lack of experimental as well as fabrication technologies. However, many efforts are now being carried out worldwide in order improve technology working at this frequency range. This book represents a mechanism to highlight some of the work being done within this range of the electromagnetic spectrum. The topics covered include non-destructive testing, teraherz imaging and sensing, among others

Analysis and Design of a Sub-THz Ultra-Wideband Phased-Array Transmitter

This thesis investigates circuits and systems for broadband high datarate transmitter systems in the millimeter-wave (mm-wave) spectrum. During the course of this dissertation, the design process and characterization of a power efficient and wideband binary phase-shift keying (BPSK) transmitter integrated circuit (IC) with local oscillator (LO) frequency multiplication and 360° phase control for beam steering is studied. All required circuit blocks are designed based on the theoretical analysis of the underlying principles, optimized, fabricated and characterized in the research laboratory targeting low power consumption, high efficiency and broadband operation. The phase-controlled push-push (PCPP) architecture enabling frequency multiplication by four in a single stage is analytically studied and characterized finding an optimum between output power and second harmonic suppression depending on the input amplitude. A PCPP based LO chain is designed. A circuit is fabricated establishing the feasibility of this architecture for operation at more than 200 GHz. Building on this, a second circuit is designed, which produces among the highest saturated output powers at 2 dBm. At less than 100 mW of direct current (DC) power consumption, this results in a power-added efficiency (PAE) of 1.6 % improving the state of the art by almost 30 %. Phase-delayed and time-delayed approaches to beam steering are analyzed, identifying and discussing design challenges like area consumption, signal attenuation and beam squint. A 60 GHz active vector-sum phase-shifter with high gain of 11.3 dB and output power of 5 dBm, improving the PAE of the state of the art by a factor of 30 achieving 6.29 %, is designed. The high gain is possible due to an optimization of the orthogonal signal creation stage enabled by studying and comparing different architectures leading to a trade off of lower signal attenuation for higher area consumption in the chosen electromagnetic coupler. By combining this with a frequency quadrupler, a phase steering enabled LO chain for operation at 220 GHz is created and characterized, confirming the preceding analysis of the phase-frequency relation during multiplication. It achieves a power gain of 21 dB, outperforming comparable designs by 25 dB. This allows the combination of phase control, frequency multiplication and pre-amplification. The radio frequency (RF) efficiency is increased 40-fold to 0.99 %, with a total power consumption of 105 mW. Motivated by the distorting effect of beam squint in phase-delayed broadband array systems, a novel analog hybrid beam steering architecture is devised, combining phase-delayed and time-delayed steering with the goal of reducing the beam squint of phase-delayed systems and large area consumption of time-delayed circuits. An analytical design procedure is presented leading to the research finding of a beam squint reduction potential of more than 83 % in an ideal system. Here, the increase in area consumption is outweighed by the reduction in beam squint. An IC with a low power consumption of 4.3 mW has been fabricated and characterized featuring the first time delay circuit operating at above 200 GHz. By producing most of the beam direction by means of time delay the beam squinting can be reduced by more than 75 % in measurements while the subsequent phase shifter ensures continuous beam direction control. Together, the required silicon area can be reduced to 43 % compared to timedelayed systems in the same frequency range. Based on studies of the optimum signal feeding and input matching of a Gilbert cell, an ultra-wideband, low-power mixer was designed. A bandwidth of more than 100 GHz was achieved exceeding the state of the art by 23 %. With a conversion gain of –13 dB, this enables datarates of more than 100 Gbps in BPSK operation. The findings are consolidated in an integrated transmitter operating around 246 GHz doubling the highest published measured datarates of transmitters with LO chain and power amplifier in BPSK operation to 56 Gbps. The resulting transmitter efficiency of 7.4 pJ/bit improves the state of the art by 70 % and 50 % over BPSK and quadrature phaseshift keying (QPSK) systems, respectively. Together, the results of this work form the basis for low-power and efficient next-generation wireless applications operating at many times the datarates available today.:Abstract 3 Zusammenfassung 5 List of Symbols 11 List of Acronyms 17 Prior Publications 19 1. Introduction 21 1.1. Motivation........................... 21 1.2. Objective of this Thesis ................... 25 1.3. Structure of this Thesis ................... 27 2. Overview of Employed Technologies and Techniques 29 2.1. IntegratedCircuitTechnology................ 29 2.2. Transmission Lines and Passive Structures . . . . . . . . 35 2.3. DigitalModulation ...................... 41 3. Frequency Quadrupler 45 3.1. Theoretical Analysis of Frequency Multiplication Circuits 45 3.2. Phase-Controlled Push-Push Principle for Frequency Quadrupling.......................... 49 3.3. Stand-alone Phase-Controlled Push-Push Quadrupler . 60 3.4. Phase-Controlled Push-Push Quadrupler based LO-chain with High Output Power ............... 72 9 4. Array Systems and Dynamic Beam Steering 91 4.1. Theoretical Analysis of BeamSteering. . . . . . . . . . . 95 4.2. Local Oscillator Phase Shifting with Vector-Modulator PhaseShifters......................... 107 4.3. Hybrid True-Time and Phase-Delayed Beam Steering . 131 5. Ultra-Wide Band Modulator for BPSK Operation 155 6. Broadband BPSK Transmitter System for Datarates up to 56 Gbps 167 6.1. System Architecture ..................... 168 6.2. Measurement Technique and Results . . . . . . . . . . . 171 6.3. Summary and performance comparison . . . . . . . . . 185 7. Conclusion and Outlook 189 A. Appendix 195 Bibliography 199 List of Figures 227 Note of Thanks 239 Curriculum Vitae 241Diese Dissertation untersucht Schaltungen und Systeme für breitbandige Transmittersysteme mit hoher Datenrate im Millimeterwellen (mm-wave) Spektrum. Im Rahmen dieser Arbeit werden der Entwurfsprozess und die Charakterisierung eines leistungseffizienten und breitbandigen integrierten Senders basierend auf binärer Phasenumtastung (BPSK) mit Frequenzvervielfachung des Lokaloszillatorsignals und 360°-Phasenkontrolle zur Strahlsteuerung untersucht. Alle erforderlichen Schaltungsblöcke werden auf Grundlage von theoretischen Analysen der zugrundeliegenden Prinzipien entworfen, optimiert, hergestellt und im Forschungslabor charakterisiert, mit den Zielen einer niedrigen Leistungsaufnahme, eines hohen Wirkungsgrades und einer möglichst großen Bandbreite. Die phasengesteuerte Push-Push (PCPP)-Architektur, welche eine Frequenzvervierfachung in einer einzigen Stufe ermöglicht, wird analytisch untersucht und charakterisiert. Dabei wird ein Optimum zwischen Ausgangsleistung und Unterdrückung der zweiten Harmonischen des Eingangssignals in Abhängigkeit von der Eingangsamplitude gefunden. Es wird eine LO-Kette auf PCPP-Basis entworfen. Eine Schaltung wird präsentiert, die die Machbarkeit dieser Architektur für den Betrieb bei mehr als 200 GHz nachweist. Darauf aufbauend wird eine zweite Schaltung entworfen, die mit 2 dBm eine der höchsten publizierten gesättigten Ausgangsleistungen erzeugt. Mit einer Leistungsaufnahme von weniger als 100mW ergibt sich ein Leistungswirkungsgrad (PAE) von 1.6 %, was den Stand der Technik um fast 30 % verbessert. Es werden phasenverzögerte und zeitverzögerte Ansätze zur Steuerung der Strahlrichtung analysiert, wobei Entwicklungsherausforderungen wie Flächenverbrauch, Signaldämpfung und Strahlschielen identifiziert und diskutiert werden. Ein aktiver Vektorsummen-Phasenschieber mit hoher Verstärkung von 11.3 dB und einer Ausgangsleistung von 5 dBm, der mit einer PAE von 6.29 % den Stand der Technik um den Faktor 30 verbessert, wird entworfen. Die hohe Verstärkung ist zum Teil auf eine Optimierung der orthogonalen Signalerzeugungsstufe zurückzuführen, die durch die Untersuchung und den Vergleich verschiedener Architekturen ermöglicht wird. Bei der Entscheidung für einen elektromagnetischen Koppler rechtfertigt die geringere Signaldämpfung einen höheren Flächenverbrauch. Durch die Kombination mit einem Frequenzvervierfacher wird eine LO-Kette mit Phasensteuerung für den Betrieb bei 220 GHz geschaffen und charakterisiert, was die vorangegangene Analyse der Phasen-FrequenzBeziehung während der Multiplikation bestätigt. Sie erreicht einen Leistungsgewinn von 21 dB und übertrifft damit vergleichbare Designs um 25dB. Dies ermöglicht die Kombination von Phasensteuerung, Frequenzvervielfachung und Vorverstärkung. Der HochfrequenzWirkungsgrad wird um das 40-fache auf 0.99 % bei einer Gesamtleistungsaufnahme von 105 mW gesteigert. Motiviert durch den verzerrenden Effekt des Strahlenschielens in phasengesteuerten Breitbandarraysystemen, wird eine neuartige analoge hybride Strahlsteuerungsarchitektur untersucht, die phasenverzögerte und zeitverzögerte Steuerung kombiniert. Damit wird sowohl das Strahlenschielen phasenverzögerter Systeme als auch der große Flächenverbrauch zeitverzögerter Schaltungen reduziert. Es wird ein analytisches Entwurfsverfahren vorgestellt, das zu dem Forschungsergebnis führt, dass in einem idealen System ein Potenzial zur Reduktion des Strahlenschielens von mehr als 83 % besteht. Dabei wird die Zunahme des Flächenverbrauchs durch die Verringerung des Strahlenschielens aufgewogen. Es wird ein IC mit einer geringen Leistungsaufnahme von 4.3mW hergestellt und charakterisiert. Dabei wird die erste Zeitverzögerungsschaltung entworfen, die bei über 200 GHz arbeitet. Durch die Erzeugung eines Großteils der Strahlrichtung mittels Zeitverzögerung kann das Schielen des Strahls bei Messungen um mehr als 75% reduziert werden, während der nachfolgende Phasenschieber eine kontinuierliche Steuerung der Strahlrichtung gewährleistet. Insgesamt kann die benötigte Siliziumfläche im Vergleich zu zeitverzögerten Systemen im gleichen Frequenzbereich auf 43 % reduziert werden. Auf der Grundlage von Studien zur optimalen Signaleinspeisung und Eingangsanpassung einer Gilbert-Zelle wird ein Ultrabreitband-Mischer mit geringem Stromverbrauch entworfen. Dieser erreicht eine Ausgangsbandbreite von mehr als 100 GHz, die den Stand der Technik um 23% übertrifft. Bei einer Wandlungsverstärkung von –13dB ermöglicht dies Datenraten von mehr als 100 Gbps im BPSK-Betrieb. Die Erkenntnisse werden in einem integrierten, breitbandigen Sender konsolidiert, der um 246 GHz arbeitet und die höchsten veröffentlichten gemessenen Datenraten für Sender mit LO-Signalkette und Leistungsverstärker im BPSK-Betrieb auf 56 Gbps verdoppelt. Die daraus resultierende Transmitter-Effizienz von 7.4 pJ/bit verbessert den Stand der Technik um 70 % bzw. 50 % gegenüber BPSKund Quadratur Phasenumtastung (QPSK)-Systemen. Zusammen bilden die Ergebnisse dieser Arbeit die Grundlage für stromsparende, effiziente, mobile Funkanwendungen der nächsten Generation mit einem Vielfachen der heute verfügbaren Datenraten.:Abstract 3 Zusammenfassung 5 List of Symbols 11 List of Acronyms 17 Prior Publications 19 1. Introduction 21 1.1. Motivation........................... 21 1.2. Objective of this Thesis ................... 25 1.3. Structure of this Thesis ................... 27 2. Overview of Employed Technologies and Techniques 29 2.1. IntegratedCircuitTechnology................ 29 2.2. Transmission Lines and Passive Structures . . . . . . . . 35 2.3. DigitalModulation ...................... 41 3. Frequency Quadrupler 45 3.1. Theoretical Analysis of Frequency Multiplication Circuits 45 3.2. Phase-Controlled Push-Push Principle for Frequency Quadrupling.......................... 49 3.3. Stand-alone Phase-Controlled Push-Push Quadrupler . 60 3.4. Phase-Controlled Push-Push Quadrupler based LO-chain with High Output Power ............... 72 9 4. Array Systems and Dynamic Beam Steering 91 4.1. Theoretical Analysis of BeamSteering. . . . . . . . . . . 95 4.2. Local Oscillator Phase Shifting with Vector-Modulator PhaseShifters......................... 107 4.3. Hybrid True-Time and Phase-Delayed Beam Steering . 131 5. Ultra-Wide Band Modulator for BPSK Operation 155 6. Broadband BPSK Transmitter System for Datarates up to 56 Gbps 167 6.1. System Architecture ..................... 168 6.2. Measurement Technique and Results . . . . . . . . . . . 171 6.3. Summary and performance comparison . . . . . . . . . 185 7. Conclusion and Outlook 189 A. Appendix 195 Bibliography 199 List of Figures 227 Note of Thanks 239 Curriculum Vitae 24