ULTRA-LOW-JITTER, MMW-BAND FREQUENCY SYNTHESIZERS BASED ON A CASCADED ARCHITECTURE

Department of Electrical EngineeringThis thesis presents an ultra-low-jitter, mmW-band frequency synthesizers based on a cascaded architecture. First, the mmW-band frequency synthesizer based on a CP PLL is presented. At the first stage, the CP PLL operating at GHz-band frequencies generated low-jitter output signals due to a high-Q VCO. At the second stage, an ILFM operating at mmW-band frequencies has a wide injection bandwidth, so that the jitter performance of the mmW-band output signals is determined by the GHz-range PLL. The proposed ultra-low-jitter, mmW-band frequency synthesizer based on a CP PLL, fabricated in a 65-nm CMOS technology, generated output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 206 fs and an IPN of ???31 dBc. The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively. However, due to a large in-band phase noise contribution of a PFD and a CP in the CP PLL, this first stage was difficult to achieve an ultra-low in-band phase noise. Second, to improve the in-band phase noise further, the mmW-band frequency synthesizer based on a digital SSPLL is presented. At the first stage, the digital SSPLL operating at GHz-band frequencies generated ultra-low-jitter output signals due to its sub-sampling operation and a high-Q GHz VCO. To minimize the quantization noise of the voltage quantizer in the digital SSPLL, this thesis presents an OSVC as a voltage quantizer while a small amount of power was consumed. The proposed ultra-low-jitter, mmW-band frequency synthesizer fabricated in a 65-nm CMOS technology, generated output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 77 fs and an IPN of ???40 dBc. The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively.clos

Array Architectures and Physical Layer Design for Millimeter-Wave Communications Beyond 5G

Ever increasing demands in mobile data rates have resulted in exploration of millimeter-wave (mmW) frequencies for the next generation (5G) wireless networks. Communications at mmW frequencies is presented with two keys challenges. Firstly, high propagation loss requires base stations (BSs) and user equipment (UEs) to use a large number of antennas and narrow beams to close the link with sufficient received signal power. Consequently, communications using narrow beams create a new challenge in channel estimation and link establishment based on fine angular probing. Current mmW system use analog phased arrays that can probe only one angle at the time which results in high latency during link establishment and channel tracking. It is desirable to design low latency beam training by exploring both physical layer designs and array architectures that could replace current 5G approaches and pave the way to the communications for frequency bands in higher mmW band and sub-THz region where larger antenna arrays and communications bandwidth can be exploited. To this end, we propose a novel signal processing techniques exploiting unique properties of mmW channel, and show both theoretically, in simulation and experiments its advantages over conventional approaches. Secondly, we explore different array architecture design and analyze their trade-offs between spectral efficiency and power consumption and area. For comprehensive comparison, we have developed a methodology for optimal design of system parameters for different array architecture candidates based on the spectral efficiency target, and use these parameters to estimate the array area and power consumption based on the circuits reported in the literature. We show that the hybrid analog and digital architectures have severe scalability concerns in radio frequency signal distribution with increased array size and spatial multiplexing levels, while the fully-digital array architectures have the best performance and power/area trade-offs.The developed approaches are based on a cross-disciplinary research that combines innovation in model based signal processing, machine learning, and radio hardware. This work is the first to apply compressive sensing (CS), a signal processing tool that exploits sparsity of mmW channel model, to accelerate beam training of mmW cellular system. The algorithm is designed to address practical issues including the requirement of cell discovery and synchronization that involves estimation of angular channel together with carrier frequency offset and timing offsets. We have analyzed the algorithm performance in the 5G compliant simulation and showed that an order of magnitude saving is achieved in initial access latency for the desired channel estimation accuracy. Moreover, we are the first to develop and implement a neural network assisted compressive beam alignment to deal with hardware impairments in mmW radios. We have used 60GHz mmW testbed to perform experiments and show that neural networks approach enhances alignment rate compared to CS. To further accelerate beam training, we proposed a novel frequency selective probing beams using the true-time-delay (TTD) analog array architecture. Our approach utilizes different subcarriers to scan different directions, and achieves a single-shot beam alignment, the fastest approach reported to date. Our comprehensive analysis of different array architectures and exploration of emerging architectures enabled us to develop an order of magnitude faster and energy efficient approaches for initial access and channel estimation in mmW systems

Design and investigation of nanometric integrated circuits for all-digital frequency synthesisers

Disertacijoje nagrinėjami daugiajuosčių dažnio sintezatorių blokai, modeliai bei jų kūrimas taikant nanometrines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad taikant nanometrines technologijas visiškai skaitmeniniai dažnio sintezatoriai įgalina gauti parametrus, reikiamus daugiajuosčiams belai- džio ryšio siųstuvams-imtuvams. Darbo tikslas – sukurti visiškai skaitmeninio dažnio sintezatoriaus blokus, kuriuos naudojant galima pasiekti reikiamus sinte- zatoriaus, skirto daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams, paramet- rus taikant nanometrines integrinių grandynų gamybos technologijas. Darbe išsp- ręsti tokie uždaviniai: ištirtos dažnio sintezatorių struktūros ir sukurta struktūra, tinkama įgyvendinti taikant nanometrines technologijas, sukurti ir ištirti siūlomos struktūros sintezatorių sudarančių blokų modeliai ir integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatū- ros ir autoriaus publikacijų disertacijos tema sąrašai ir keturi priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašo- mas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma ty- rimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, gi- namieji teiginiai bei disertacijos struktūra. Pirmajame skyriuje apžvelgiamos dažnio sintezatorių rūšys, aprašomi pag- rindiniai dažnio sintezatorių parametrai ir dažniausiai naudojamos kokybės funk- cijos. Apžvelgiami dažnio sintezatorių modeliai ir jų veikimas fazės ir dažnio sri- tyse. Aprašomi visiškai skaitmeninio dažnio sintezatoriaus triukšmų šaltiniai. Skyriaus pabaigoje suformuluojami disertacijos uždaviniai. Antrajame skyriuje pasiūlyta ir taikoma nauja kokybės funkcija, leidžianti at- likti daugiajuosčių dažnio sintezatorių palyginamąją analizę. Iškeliami reikalavi- mai pagrindiniams sintezatoriaus blokams, nagrinėjami laikinio skaitmeninio kei- tiklio skiriamosios gebos didinimo būdai, sukurtas naujas laikinio skaitmeninio keitiklio modelis. Siūloma dažnio sintezatoriaus struktūra daugiajuosčiams siųs- tuvams-imtuvams. Trečiajame skyriuje pagal iškeltus reikalavimus daugiajuosčio dažnio sinte- zatoriaus blokams, taikant kompiuterinių skaičiavimų ir eksperimentinius meto- dus yra kuriami ir tiriami laikinio skaitmeninio keitiklio, skaitmeniniu būdu val- domo generatoriaus bei skaitmeninio filtro integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 4 – mokslo žurna- luose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 1 – tarp- tautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analytics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duo- menų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti devyniose mokslinėse konferencijose Lietuvoje ir užsienyje

High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion

The purpose of this thesis is the proposal and implementation of data conversion open-loop architectures based on voltage-controlled oscillators (VCOs) built with ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to the newest complementary metal-oxide-semiconductor (CMOS) nodes. The scaling of the design technologies into the nanometer range imposes the reduction of the supply voltage towards small and power-efficient architectures, leading to lower voltage overhead of the transistors. Additionally, phenomena like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between devices and PVT variations) make the design of classic structures for ADCs more challenging. In recent years, time-encoded A/D conversion has gained relevant popularity due to the possibility of being implemented with mostly digital structures. Within this trend, VCOs designed with ring oscillator based topologies have emerged as promising candidates for the conception of new digitization techniques. RO-based data converters show excellent scalability and sensitivity, apart from some other desirable properties, such as inherent quantization noise shaping and implicit anti-aliasing filtering. However, their nonlinearity and the limited time delay achievable in a simple NOT gate drastically limits the resolution of the converter, especially if we focus on wide-band A/D conversion. This thesis proposes new ways to alleviate these issues. Firstly, circuit-based techniques to compensate for the nonlinearity of the ring oscillator are proposed and compared to equivalent state-of-the-art solutions. The proposals are designed and simulated in a 65-nm CMOS node for open-loop RO-based ADC architectures. One of the techniques is also validated experimentally through a prototype. Secondly, new ways to artificially increase the effective oscillation frequency are introduced and validated by simulations. Finally, new approaches to shape the quantization noise and filter the output spectrum of a RO-based ADC are proposed theoretically. In particular, a quadrature RO-based band-pass ADC and a power-efficient Nyquist A/D converter are proposed and validated by simulations. All the techniques proposed in this work are especially devoted for highbandwidth applications, such as Internet-of-Things (IoT) nodes or maximally digital radio receivers. Nevertheless, their field of application is not restricted to them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas de conversión de datos basadas en osciladores en anillos, compatibles con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación más modernos donde las estructuras digitales se ven favorecidas. La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción de la tensión de alimentación para el desarrollo de arquitecturas pequeñas y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión para saturar transistores, lo que añadido a una ganancia cada vez menor de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones de proceso, tensión y temperatura han llevado a que sea cada vez más complejo el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión A/D basada en codificación temporal ha ganado gran popularidad dado que permite la implementación de estructuras mayoritariamente digitales. Como parte de esta evolución, los osciladores controlados por tensión diseñados con topologías de oscilador en anillo han surgido como un candidato prometedor para la concepción de nuevas técnicas de digitalización. Los convertidores de datos basados en osciladores en anillo son extremadamente sensibles (variación de frecuencia con respecto a la señal de entrada) así como escalables, además de otras propiedades muy atractivas, como el conformado espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta NOT restringen la resolución del conversor, especialmente para conversión A/D en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas técnicas para aliviar este tipo de problemas. En primer lugar, se proponen técnicas basadas en circuito para compensar el efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas presentadas es también validada experimentalmente a través de un prototipo. En segundo lugar, se introducen y validan por simulación varias formas de incrementar artificialmente la frecuencia de oscilación efectiva. Para finalizar, se proponen teóricamente dos enfoques para configurar nuevas formas de conformación del ruido de cuantificación y filtrado del espectro de salida de los datos digitales. En particular, son propuestos y validados por simulación un ADC pasobanda en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente para aplicaciones de alto ancho de banda, tales como módulos para el Internet de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar de ello, son extrapolables también a otros campos como el de la instrumentación biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí

Synthèses de fréquence à bas bruit basées sur des oscillateurs opto-électroniques couplés intégrées en technologie BiCMOS SiGe 130nm

Les hyperfréquences jouent un rôle indispensable dans le domaine des télécommunications, que ce soit pour la téléphonie mobile, les radars automobiles, le Wi-Fi ou encore la transmission satellitaire, sans que cette liste ne soit évidemment exhaustive. Pour l'ensemble de ces applications omniprésentes dans la société actuelle, ce sont ces signaux hyperfréquences qui servent de porteuses pour transmettre l'information sur de plus ou moins longues distances. Les méthodes de génération de signaux hyperfréquences actuelles sont basées sur des boucles à verrouillage de phase (PLL). Elles réalisent une multiplication d'une fréquence de référence basse de quelques dizaines à quelques centaines de mégahertz pour l'amener à quelques gigahertz voire dizaines de gigahertz. Il y a cependant un inconvénient majeur lié à cette méthode : synthétiser une fréquence par multiplication d'une référence basse s'accompagne d'une augmentation théorique du bruit de phase du signal généré, d'autant plus que le rapport de multiplication est élevé. À l'inverse, une synthèse par division de fréquence diminue le bruit de phase théorique. Or on voit apparaître depuis quelques années des références à des fréquences déjà élevées, basées sur des oscillateurs optoélectroniques couplés (COEO), qui peuvent dès lors servir à réaliser des synthèses basées sur de la division de fréquence, et c'est dans ce cadre que se situe le travail de cette thèse. Nous utilisons pour référence de fréquence, des COEO qui génèrent un signal de fréquence élevée à haute pureté spectrale, à 10 et 30 GHz. L'objectif est alors d'être capable de générer des signaux dont la fréquence est inférieure à 30 GHz et aussi basse que 1 GHz. Ces signaux synthétisés doivent conserver autant que possible la pureté spectrale du signal de référence en pénalisant le moins possible le bénéfice théorique apporté par la division. Cette thèse décrit la conception de diviseurs hyperfréquences à très faible bruit de phase résiduel disposant au final de rapports de division fractionnaires et/ou programmables. Dans un premier temps, nous avons conçu des diviseurs de rapports fixes afin d'estimer les performances en bruit de phase atteignables à cette fréquence de travail sur les technologies utilisées. Plusieurs diviseurs ECL par 2 et par 3 ont été conçus, fabriqués et mesurés pour une division jusqu'à 30 GHz. Un diviseur CMOS par 10 ainsi qu'une technique de resynchronisation permettant d'annuler la majeure partie du bruit de phase de la chaîne de division sont également présentés. Plusieurs diviseurs analogiques à rang fixe ont également été conçus, bien que s'étant révélés moins performants au final : un diviseur à verrouillage par injection (ILFD) et un diviseur à renforcement du second harmonique, qui réalisent tous les deux une division par 3 autour de 30 GHz. Pour terminer, nous avons conçu des diviseurs fractionnaires large bande fonctionnant au moins jusqu'à 30 GHz et offrant des performances en bruit de phase compétitives. Si ces modèles s'inspirent du principe régénératif connu de Miller, nous en proposons une déclinaison tout à fait originale. Une première série de diviseurs fractionnaires fixes a ainsi été réalisée pour des rapports fixes de 1,25, 2,5 et 4,5. Pour terminer, un diviseur fractionnaire dont la partie décimale est programmable a été ensuite été réalisé et mesuré. Il s'agit d'un diviseur fractionnaire dont la partie entière du rapport de division est 4 et la partie décimale codée sur 4 bits.Microwave signals are essential in the field of telecommunications whether for mobile telephony, automotive radar, Wi-Fi or even satellite transmission, without this list being exhaustive. For all these ubiquitous applications in our current society, microwave signals are the carriers for the transmission of information from a system to another. Microwave signals synthesis techniques are mostly based on Phase-Locked Loop (PLL). PLL multiply a low frequency reference ranging from a dozen to a few hundred megahertz toward a few gigahertz to a few dozen gigahertz. However, there is one main drawback with this synthesis technique: synthesizing a frequency by multiplying a low frequency reference induces an unavoidable rise of the theoretical phase noise of the synthesized signal, even more if the multiplication factor is high. On the contrary, frequency synthesis by division lowers the theoretical phase noise. Yet, high frequency high spectral purity frequency references called Coupled OptoElectronic Oscillator (COEO) are being developed for a few years. They are perfect candidate to be used as reference for frequency synthesis by division, and this is within this framework that our research takes place. We use as frequency references two COEO generating high spectral purity signals at 10 and 30?GHz. The aim of our work is then to be able to generate different signals whose frequencies are below 30?GHz and as low as 1?GHz. These synthesized signals must preserve as much as possible the spectral purity of the reference while deteriorating as less as possible the theoretical benefit brought by the division. This thesis describes the conception of low residual phase noise microwave frequency dividers operating, for the most evolved ones, fractional and/or programmable division ratios. In a first place, we designed static frequency dividers in order to estimate the phase noise performance that we can conceivably reach with the technology we use. Several ECL dividers by 2 and by 3 are designed, fabricated and measured for a division up to 30?GHz. A CMOS divider by 10 along with a resynchronization technique allowing to cancel most of the phase noise in a cascaded divider are also presented. In a second place, we designed analog dividers, although they have proven to be less competitive than digital dividers: an Injection-Locked Frequency Divider (ILFD) and a regenerative second-harmonic frequency divider, both realising a frequency division by 3 around 30 GHz. Finally, we designed wideband fractional dividers operating at least at 30 GHz with competitive phase noise performance. Even though they are inspired by Miller's regenerative frequency dividers, we introduce here an innovative declination of fractional dividers. A first series of static fractional dividers has been designed with ratios of 1.25, 2.5 and 4.5. Ultimately, a fractional divider with a programmable decimal part has been designed and measured. This divider has an integer part of 4 and a decimal part programmed on 4 bits

MEMS Accelerometers

Micro-electro-mechanical system (MEMS) devices are widely used for inertia, pressure, and ultrasound sensing applications. Research on integrated MEMS technology has undergone extensive development driven by the requirements of a compact footprint, low cost, and increased functionality. Accelerometers are among the most widely used sensors implemented in MEMS technology. MEMS accelerometers are showing a growing presence in almost all industries ranging from automotive to medical. A traditional MEMS accelerometer employs a proof mass suspended to springs, which displaces in response to an external acceleration. A single proof mass can be used for one- or multi-axis sensing. A variety of transduction mechanisms have been used to detect the displacement. They include capacitive, piezoelectric, thermal, tunneling, and optical mechanisms. Capacitive accelerometers are widely used due to their DC measurement interface, thermal stability, reliability, and low cost. However, they are sensitive to electromagnetic field interferences and have poor performance for high-end applications (e.g., precise attitude control for the satellite). Over the past three decades, steady progress has been made in the area of optical accelerometers for high-performance and high-sensitivity applications but several challenges are still to be tackled by researchers and engineers to fully realize opto-mechanical accelerometers, such as chip-scale integration, scaling, low bandwidth, etc