Ultra-Low Power Circuit Design for Cubic-Millimeter Wireless Sensor Platform.

Modern daily life is surrounded by smaller and smaller computing devices. As Bell’s Law predicts, the research community is now looking at tiny computing platforms and mm3-scale sensor systems are drawing an increasing amount of attention since they can create a whole new computing environment. Designing mm3-scale sensor nodes raises various circuit and system level challenges and we have addressed and proposed novel solutions for many of these challenges to create the first complete 1.0mm3 sensor system including a commercial microprocessor. We demonstrate a 1.0mm3 form factor sensor whose modular die-stacked structure allows maximum volume utilization. Low power I2C communication enables inter-layer serial communication without losing compatibility to standard I2C communication protocol. A dual microprocessor enables concurrent computation for the sensor node control and measurement data processing. A multi-modal power management unit allowed energy harvesting from various harvesting sources. An optical communication scheme is provided for initial programming, synchronization and re-programming after recovery from battery discharge. Standby power reduction techniques are investigated and a super cut-off power gating scheme with an ultra-low power charge pump reduces the standby power of logic circuits by 2-19× and memory by 30%. Different approaches for designing low-power memory for mm3-scale sensor nodes are also presented in this work. A dual threshold voltage gain cell eDRAM design achieves the lowest eDRAM retention power and a 7T SRAM design based on hetero-junction tunneling transistors reduces the standby power of SRAM by 9-19× with only 15% area overhead. We have paid special attention to the timer for the mm3-scale sensor systems and propose a multi-stage gate-leakage-based timer to limit the standard deviation of the error in hourly measurement to 196ms and a temperature compensation scheme reduces temperature dependency to 31ppm/°C. These techniques for designing ultra-low power circuits for a mm3-scale sensor enable implementation of a 1.0mm3 sensor node, which can be used as a skeleton for future micro-sensor systems in variety of applications. These microsystems imply the continuation of the Bell’s Law, which also predicts the massive deployment of mm3-scale computing systems and emergence of even smaller and more powerful computing systems in the near future.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91438/1/sori_1.pd

A 1.1 nW Energy-Harvesting System with 544 pW Quiescent Power for Next-Generation Implants

This paper presents a nW power management unit (PMU) for an autonomous wireless sensor that sustains itself by harvesting energy from the endocochlear potential (EP), the 70-100 mV electrochemical bio-potential inside the mammalian ear. Due to the anatomical constraints inside the inner ear, the total extractable power from the EP is limited close to 1.1-6.25 nW. A nW boost converter is used to increase the input voltage (30-55 mV) to a higher voltage (0.8-1.1 V) usable by CMOS circuits in the sensor. A pW charge pump circuit is used to minimize the leakage in the boost converter. Furthermore, ultralow-power control circuits consisting of digital implementations of input impedance adjustment circuits and zero current switching circuits along with Timer and Reference circuits keep the quiescent power of the PMU down to 544 pW. The designed boost converter achieves a peak power conversion efficiency of 56%. The PMU can sustain itself, and a duty-cyled ultralow-power load while extracting power from the EP of a live guinea pig. The PMU circuits have been implemented on a 0.18- μm CMOS process.Semiconductor Research Corporation. Focus Center for Circuit and System Solutions (C2S2)Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation)National Institutes of Health (U.S.) (Grant K08 DC010419)National Institutes of Health (U.S.) (Grant T32 DC00038)Bertarelli Foundatio

Ultra-Low-Power Wake-up Clock Design for SoC Applications

This thesis studies how to design an ultra-low-power wake-up clock circuit for SoCapplications that essentially consists of a resistor based reference circuit, switched-capacitor branch, an ultra-low-power amplifier, a VCO and a non-overlapping clockphase generator circuit. The circuit is designed in 180-nm CMOS technology usingCAD software for circuit design, layout design, pre and post-layout simulations.At first, a brief study of different clock-generation circuit architectures is made,wherein their merits and de-merits are discussed. This is followed by a study ofan ultra-low-power amplifier, ring-oscillator-based VCO, non-overlapping clockcircuits, the bias generation circuit and the current reference circuit. Additionally,a reference current chopping technique that further improves temperature stabilityis also described. Later, the report discusses the design and simulations of theactual implementation. Analysis of the design with regards to power consumption,temperature stability and layout area are carried out. The circuit operates at8.254kHz consuming 70.4nW with a temperature stability of 7.35ppm/◦C in thetemperature range of -40◦C to 75◦C. The final layout takes an area of 0.153mm2.The final design is analysed for its functionality at various process, voltage andtemperature corners. Future improvements in the current design are also discussedat the end of this report

Ultra Low Power Analog Circuits for Wireless Sensor Node System.

This thesis will discuss essential analog circuit blocks required in ultra-low power wireless sensor node systems. A wireless sensor network system requires very high energy and power efficiency which is difficult to achieve with traditional analog circuits. First, 5.58nW real time clock using a DLL (Delay Locked Loop)-assisted pulse-driven crystal oscillator is discussed. In this circuit, the operational amplifier used in the traditional circuit was replaced with pulsed drivers. The pulse was generated at precise timing by a DLL. The circuit parts operate in different supply levels, generated on chip by using a switched capacitor network. The circuit was tested at different supply voltage and temperature. Its frequency characteristic along with power consumption were measured and compared to the traditional circuit. Next, a Schmitt trigger based pulse-driven crystal oscillator is discussed. In the first chapter, a DLL was used to generate a pulse with precise timing. However, testing results and recent study showed that the crystal oscillator can sustain oscillation even with inaccurate pulse timing. In this chapter, pulse location is determined by the Schmitt trigger. Simulation results show that this structure can still sustain oscillation at different process corners and temperature. In the next chapter, a sub-nW 8 bit SAR ADC (Successive Approximation Analog-to-Digital Converter) using transistor-stack DAC (Digital-to-Analog Converter) is discussed. To facilitate design effort and reduce the layout dependent effect, a conventional capacitive DAC was replaced with transistor-stack DAC with a 255:1 multiplexer. The control logic was designed with both TSPC (True Single Phase Clock) and CMOS logic to minimize transistor count. The ADC was implemented in a 65nm CMOS process and tested at different sampling rates and input signal frequency. Its linearity and power consumption was measured. Also, a similar design was implemented and tested using 180nm CMOS process as part of a sensor node system. Lastly, a multiple output level voltage regulator using a switched capacitor network for low-cost system is discussed.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111626/1/dmyoon_1.pd

Energy efficient control for power management circuits operating from nano-watts to watts

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 163-172).Energy efficiency and form factor are the key driving forces in today's power electronics. All power delivery circuits, irrespective of the magnitude of power, basically consists of power trains, gate drivers and control circuits. Although the control circuits are primarily required for regulation, these circuits can play a crucial role in achieving high efficiency and/or minimizing overall system form-factor. In this thesis, power converter circuits, spanning a wide operating range- from nano-watts to watts, are presented while highlighting techniques for using digital control circuits not just for regulation but also to achieve high system efficiency and smaller system form-factor. The first part of the thesis presents a power management unit of an autonomous wireless sensor that sustains itself by harvesting energy from the endo-cochlear potential (EP), the 70-100mV electrochemical potential inside the mammalian inner ear. Due to the anatomical constraints, the total extractable power from the EP is limited to 1.1-6.3nW. A low switching frequency boost converter is employed to increase the input voltage to a higher voltage usable by CMOS circuits in the sensor. Ultra-low power digital control circuits with timers help keep the quiescent power of the power management unit down to 544pW. Further, a charge-pump is used to implement leakage reduction techniques in the sensor. This work demonstrates how digital low power control circuit design can help improve converter efficiency and ensure system sustainability. All circuits have been implemented on a 0.18[mu]m CMOS process. The second part of the thesis discusses an energy harvesting architecture that combines energy from multiple energy harvesting sources- photovoltaic, thermoelectric and piezoelectric sources. Digital control circuits that configure the power trains to new efficient system architectures with maximum power point tracking are presented, while using a single inductor to combine energy from the aforementioned energy sources all at the same time. A dual-path architecture for energy harvesting systems is proposed. This provides a peak efficiency improvement of 11-13% over the traditional two stage approach. The system can handle input voltages from 20mV to 5V and is also capable of extracting maximum power from individual harvesters all at the same time utilizing a single inductor. A proposed completely digital timebased power monitor is used for achieving maximum power point tracking for the photovoltaic harvester. This has a peak tracking efficiency of 96%. The peak efficiencies achieved with inductor sharing are 83%, 58% and 79% for photovoltaic boost, thermoelectric boost and piezoelectric buck-boost converters respectively. The switch matrix and the control circuits are implemented on a 0.35pm CMOS process. This part of the thesis highlights how digital control circuits can help reconfigure power converter architectures for improving efficiency and reducing form-factors. The last part of the thesis deals with a power management system for an offline 22W LED driver. In order to reduce the system form factor, Gallium Nitride (GaN) transistors capable of high frequency switching have been utilized with a Quasi-Resonant Inverted Buck architecture. A burst mode digital controller has been used to perform dimming control and power factor correction (PFC) for the LED driver. The custom controller and driver IC was implemented in a 0.35[mu]m CMOS process. The LED driver achieves a peak efficiency of 90.6% and a 0.96 power factor. Due to the high power level of the driver, the digital controller is primarily used for regulation purposes in this system, although the digital nature of the controller helps remove the passives that would be normally present in analog controllers. In this thesis, apart from regulation, control circuit enabled techniques have been used to improve efficiency and reduce system form factor. Low power design and control for reconfigurable power train architectures help improve the overall power converter efficiency. Digital control circuits have been used to reduce the form factor by enabling inductor sharing in a system with multiple power converters or by removing the compensator passives.by Saurav Bandyopadhyay.Ph.D