Dynamic element matching techniques for data converters

Analog to digital converter (ADC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in an ADC\u27s output. In this dissertation, two techniques for estimating an ADC\u27s output spectrum from the ADC\u27s transfer function are determined. These methods are compared to a symmetric power function and asymmetric power function approximations. Standard ADC performance metrics, such as SDR, SNDR, SNR, and SFDR, are also determined as a function of the ADC\u27s transfer function approximations. New dynamic element matching (DEM) flash ADCs are developed. An analysis of these DEM flash ADCs is developed and shows that these DEM algorithms improve an ADC\u27s performance. The analysis is also used to analyze several existing DEM ADC architectures; Digital to analog converter (DAC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in a DAC\u27s output. In this dissertation, an exact relationship between a DAC\u27s integral nonlinearity (INL) and its output spectrum is determined. Using this relationship, standard DAC performance metrics, such as SDR, SNDR, SNR, and SFDR, are calculated from the DAC\u27s transfer function. Furthermore, an iterative method is developed which determines an arbitrary DAC\u27s transfer function from observed output magnitude spectra. An analysis of DEM techniques for DACs, including the determination of several suitable metrics by which DEM techniques can be compared, is derived. The performance of a given DEM technique is related to standard DAC performance metrics, such as SDR, SNDR, and SFDR. Conditions under which DEM techniques can guarantee zero average INL and render the distortion due to mismatched components as white noise are developed. Several DEM circuits proposed in the literature are shown to be equivalent and have hardware efficient implementations based on multistage interconnection networks. Example DEM circuit topologies and their hardware efficient VLSI implementations are also presented

A 0.29 MM2 12-BIT SEGMENTED CURRENT STEERING DAC WITH DIGITALLY ASSISTED ERROR COMPENSATION GROUPING

Ph.DDOCTOR OF PHILOSOPH

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Binary Weighted DAC with 2-ξ Resistor Ratio

In this paper we present a new digital analog converter (DAC) design, based on the binary weighted resistor network. The proposed design ensures high conversion accuracy using low precision resistors with ±1% ±2%, ±5%, ±10% and ±20% resistor tolerance. High accuracy is achieved due to better coverage of the analog domain of the transfer characteristic. In binary weighted converters the imprecision of resistors introduces positive and negative differential nonlinearities (DNL). Positive DNL causes gap in the analog domain of the transfer characteristic and negative DNL causes non-monotonicity. In the proposed solution we change the resistor ratio of the two consecutive DAC branches from 2 to 2-ξ, where ξ is small positive number. With this change, we intentionally introduce an additional negative DNL in order to entirely avoid the positive gap. Simulation results confirm that even with resistors tolerance of up to ±10%, we can achieve a converter with maximal gap in the transfer characteristic less than or around one LSB

Enhanced-accuracy oversampled data converters

Digital-to-analog converters (DACs) suffer from static and dynamic nonlinearity problems, which degrade their accuracy and performance. Mismatch errors in the analog components restrict the maximum achievable linearity. This thesis presents various techniques for correcting these errors. It describes a correction process for the nonlinear behavior of DACs, on three different levels: architectural design, circuit design, and layout design. The main results achieved are listed below: • Novel topologies using stochastic approaches to linearize multibit converters are presented. • A new method is introduced for avoiding the use of multibit DACs in the main loop of multi-path DS analog-to-digital converters (ADCs), which, combined with a novel noise leakage compensation technique, allows the use of low quality inner DACs. • A novel correction algorithm is proposed, which is based on the acquisition of the individual DAC errors by means of correlation procedures. The extracted values are used for correction purposes. The technique is capable of background operation. • Different circuits are proposed to improve the performance of current-steering DACs. Also, novel layout techniques are shown for reducing the spatial variations of the unit sources. Some of the presented techniques were combined in a prototype chip, designed and fabricated in a 0.35μm CMOS process. Simulation and preliminary measurement results show that they are effective.Keywords: data converters, digital-to-analog, integrated circuits, analog-to-digital, CMO

Digital signal processing and digital-to-analog converters for wide-band transmitters

In this thesis, the implementation methods of digital signal processing and digital-to-analog converters for wide-band transmitters are researched. With digital signal processing, the problems of analog signal processing, such as sensitivity to interference and nonidealities of the semiconductor processes, can be avoided. Also, the programmability can be implemented digitally more easily than by means of analog signal processing. During the past few years, wireless communications has evolved from analog to digital, and signal bandwidths have increased, enabling faster and faster data transmission. The evolution of semiconductor processes, decreasing linewidth and supply voltages, has decreased the size of the electronics and power dissipation, enabling the integration of larger and larger systems on single silicon chips. There is little overall benefit in decreasing linewidths to meet the needs of analog design, since it makes the design process more difficult as the device sizes cannot be scaled according to minimum linewidth and because of the decreasing supply voltage. On the other hand, the challenges of digital signal processing are related to the efficient realization of signal processing algorithms in such a way that the required area and power dissipation does not increase extensively. In this book, the problems related to digital filters, upconversion algorithms and digital-to-analog converters used in digital transmitters are researched. Research results are applied to the implementation of a transmitter for a third-generation WCDMA base-station. In addition, the theory of factors affecting the linearity and performance of digital-to-analog converters is researched, and a digital calibration algorithm for enhancement of the static linearity has been presented. The algorithm has been implemented together with a 16-bit converter; its functionality has been demonstrated with measurements.Tässä väitöskirjassa on tutkittu digitaalisen signaalinkäsittelyn toteuttamista ja digitaalisesta analogiseksi -muuntimia laajakaistaisiin lähettimiin. Digitaalisella signaalinkäsittelyllä voidaan välttää monia analogiseen signaalinkäsittelyyn liittyviä ongelmia, kuten häiriöherkkyyttä ja puolijohdeprosessien epäideaalisuuksien vaikutuksia. Myös ohjelmoitavuus on helpommin toteutettavissa digitaalisesti kuin analogisen signaalinkäsittelyn keinoin. Viime vuosina on langattomien tietoliikennejärjestelmien kehitys kulkenut analogisesta digitaaliseen, ja käytettävät signaalikaistanleveydet ovat kasvaneet mahdollistaen yhä nopeamman tiedonsiirron. Puolijohdeprosessien kehitys, kapeneva minimiviivanleveys ja pienemmät käyttöjännitteet, on pienentänyt elektroniikan kokoa ja tehonkulutusta mahdollistaen yhä suurempien kokonaisuuksien integroimisen yhdelle piisirulle. Viivanleveyksien pieneneminen ei kuitenkaan suoraan hyödytä analogiasuunnittelua, jossa piirielementtien kokoa ei välttämättä voida pienentää viivanleveyden pienentyessä, ja jossa madaltuva käyttöjännite ennemminkin hankaloittaa kuin helpottaa suunnittelua. Siksi yhä suurempi osa signaalinkäsittelystä pyritään tekemään digitaalisesti. Digitaalisen signaalinkäsittelyn ongelmat puolestaan liittyvät algoritmien tehokkaaseen toteuttamiseen siten, että piirien pinta-ala ja tehonkulutus eivät kasva liian suuriksi. Tässä kirjassa on tutkittu digitaalisessa lähettimessä tarvittavien digitaalisten suodattimien, ylössekoitusalgoritmien ja digitaalisesta analogiseksi -muuntimien toteuttamiseen liittyviä ongelmia. Tutkimustuloksia on sovellettu kolmannen sukupolven WCDMA-tukiasemalähettimen toteutuksessa. Lisäksi on tutkittu digitaalisesta analogiseksi -muuntimien lineaarisuuteen ja suorituskykyyn vaikuttavien seikkojen teoriaa, ja esitetty digitaalinen kalibrointialgoritmi muuntimen staattisen suorituskyvyn parantamiseksi. Algoritmi on toteutettu 16-bittisen muuntimen yhteydessä ja se on osoitettu toimivaksi mittauksin.reviewe