Numerical analysis of Huygens-like on-chip antennas for mm-wave applications

As we transition to 5G and beyond, the frequencies increase and the efficiency of the antennas becomes a pressing issue. Silicon technologies are preferred when it comes to en masse user equipment production, but the antennas in silicon suffer from high dielectric losses and strong substrate waves coupling. The use of a Huygens source as the antenna element has a potential of decreasing these negative effects, as was demonstrated in several non-silicon PCB designs. In this paper, we investigate if a similar performance enhancement can be achieved in thin back-gated silicon antenna chips. We present a numerical comparison of an electric dipole, a magnetic dipole and a Huygens source antenna at 120 GHz on a lossy silicon substrate sitting on a ground plane. Antennas are defined in MATLAB as distributed currents and imported as near-field sources into CST Microwave Studio. This way we treat the problem in a very general way without regards for any particular physical antenna implementations. Radiation efficiency and gain are shown as functions of substrate thickness. We found that there is no apparent advantage of using a Huygens source over either electric or a magnetic dipole in the described setup. We argue that this result is based on the fact that the Huygens source is derived assuming infinite current sheets at the interface of two infinite homogeneous regions, and propose another definition for a Huygens source in multi-layer structures

Voltage controlled oscillator for mm-wave radio systems

Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology

Convergent communication, sensing and localization in 6g systems: An overview of technologies, opportunities and challenges

Herein, we focus on convergent 6G communication, localization and sensing systems by identifying key technology enablers, discussing their underlying challenges, implementation issues, and recommending potential solutions. Moreover, we discuss exciting new opportunities for integrated localization and sensing applications, which will disrupt traditional design principles and revolutionize the way we live, interact with our environment, and do business. Regarding potential enabling technologies, 6G will continue to develop towards even higher frequency ranges, wider bandwidths, and massive antenna arrays. In turn, this will enable sensing solutions with very fine range, Doppler, and angular resolutions, as well as localization to cm-level degree of accuracy. Besides, new materials, device types, and reconfigurable surfaces will allow network operators to reshape and control the electromagnetic response of the environment. At the same time, machine learning and artificial intelligence will leverage the unprecedented availability of data and computing resources to tackle the biggest and hardest problems in wireless communication systems. As a result, 6G will be truly intelligent wireless systems that will provide not only ubiquitous communication but also empower high accuracy localization and high-resolution sensing services. They will become the catalyst for this revolution by bringing about a unique new set of features and service capabilities, where localization and sensing will coexist with communication, continuously sharing the available resources in time, frequency, and space. This work concludes by highlighting foundational research challenges, as well as implications and opportunities related to privacy, security, and trust

Convergent Communication, Sensing and Localization in 6G Systems: An Overview of Technologies, Opportunities and Challenges

Herein, we focus on convergent 6G communication, localization and sensing systems by identifying key technology enablers, discussing their underlying challenges, implementation issues, and recommending potential solutions. Moreover, we discuss exciting new opportunities for integrated localization and sensing applications, which will disrupt traditional design principles and revolutionize the way we live, interact with our environment, and do business. Regarding potential enabling technologies, 6G will continue to develop towards even higher frequency ranges, wider bandwidths, and massive antenna arrays. In turn, this will enable sensing solutions with very fine range, Doppler, and angular resolutions, as well as localization to cm-level degree of accuracy. Besides, new materials, device types, and reconfigurable surfaces will allow network operators to reshape and control the electromagnetic response of the environment. At the same time, machine learning and artificial intelligence will leverage the unprecedented availability of data and computing resources to tackle the biggest and hardest problems in wireless communication systems. As a result, 6G will be truly intelligent wireless systems that will provide not only ubiquitous communication but also empower high accuracy localization and high-resolution sensing services. They will become the catalyst for this revolution by bringing about a unique new set of features and service capabilities, where localization and sensing will coexist with communication, continuously sharing the available resources in time, frequency, and space. This work concludes by highlighting foundational research challenges, as well as implications and opportunities related to privacy, security, and trust

Reconfigurable Gate Driver Toward High-Power Efficiency and High-Power Density Converters

Les systèmes de gestion de l'énergie exigent des convertisseurs de puissance pour fournir une conversion de puissance adaptée à diverses utilisations. Il existe différents types de convertisseurs de puissance, tel que les amplificateurs de puissance de classe D, les demi-ponts, les ponts complets, les amplificateurs de puissance de classe E, les convertisseurs buck et dernièrement les convertisseurs boost. Prenons par exemple les dispositifs implantables, lorsque l'énergie est prélevée de la source principale, des convertisseurs de puissance buck ou boost sont nécessaires pour traiter l'énergie de l'entrée et fournir une énergie propre et adaptée aux différentes parties du système. D'autre part, dans les stations de charge des voitures électriques, les nouveaux téléphones portables, les stimulateurs neuronaux, etc., l'énergie sans fil a été utilisée pour assurer une alimentation à distance, et des amplificateurs de puissance de classe E sont développés pour accomplir cette tâche. Les amplificateurs de puissance de classe D sont un excellent choix pour les casques d'écoute ou les haut-parleurs en raison de leur grande efficacité. Dans le cas des interfaces de capteurs, les demi-ponts et les ponts complets sont les interfaces appropriées entre les systèmes à faible et à forte puissance. Dans les applications automobiles, l'interface du capteur reçoit le signal du côté puissance réduite et le transmet à un réseau du côté puissance élevée. En outre, l'interface du capteur doit recevoir un signal du côté haute puissance et le convertir vers la côté basse puissance. Tous les systèmes mentionnés ci-dessus nécessitent l'inclusion d'un pilote de porte spécifique dans les circuits, selon les applications. Les commandes de porte comprennent généralement un décalage du niveau de commande niveau supérieur, le levier de changement de niveau inférieur, une chaîne de tampon, un circuit de verrouillage sous tension, un circuit de temps mort, des portes logiques, un inverseur de Schmitt et un mécanisme de démarrage. Ces circuits sont nécessaires pour assurer le bon fonctionnement des systèmes de conversion de puissance. Un circuit d'attaque de porte reconfigurable prendrait en charge une vaste gamme de convertisseurs de puissance ayant une tension d'entrée V[indice IN] et un courant de sortie I[indice Load] variables. L'objectif de ce projet est d'étudier intensivement les causes de différentes pertes dans les convertisseurs de puissance et de proposer ensuite de nouveaux circuits et méthodologies dans les différents circuits des conducteurs de porte pour atteindre une conversion de puissance avec une haute efficacité et densité de puissance. Nous proposons dans cette thèse de nouveaux circuits de gestion des temps mort, un Shapeshifter de niveau plus élevé et un Shapeshifter de niveau inférieur avec de nouvelles topologies qui ont été pleinement caractérisées expérimentalement. De plus, l'équation mathématique du temps mort optimal pour les faces haute et basse d'un convertisseur buck est dérivée et expérimentalement prouvée. Les circuits intégrés personnalisés et les méthodologies proposées sont validés avec différents convertisseurs de puissance, tels que les convertisseurs semi-pont et en boucle ouverte, en utilisant des composants standard pour démontrer leur supériorité sur les solutions traditionnelles. Les principales contributions de cette recherche ont été présentées à sept conférences prestigieuses, trois articles évalués par des pairs, qui ont été publiés ou présentés, et une divulgation d'invention. Une contribution importante de ce travail recherche est la proposition d'un nouveau générateur actif CMOS intégré dédié de signaux sans chevauchement. Ce générateur a été fabriqué à l'aide de la technologie AMS de 0.35µm et consomme 16.8mW à partir d'une tension d'alimentation de 3.3V pour commander de manière appropriée les côtés bas et haut d'un demi-pont afin d'éliminer la propagation. La puce fabriquée est validée de façon expérimentale avec un demi-pont, qui a été mis en œuvre avec des composants disponibles sur le marché et qui contrôle une charge R-L. Les résultats des mesures montrent une réduction de 40% de la perte totale d'un demi-pont de 45V d'entrée à 1MHz par rapport au fonctionnement du demi-pont sans notre circuit intégré dédié. Le circuit principal du circuit d'attaque de grille côté haut est le décaleur de niveau, qui fournit un signal de grande amplitude pour le commutateur de puissance côté haut. Une nouvelle structure de décalage de niveau avec un délai de propagation minimal doit être présentée. Nous proposons une nouvelle topologie de décalage de niveau pour le côté haut des drivers de porte afin de produire des convertisseurs de puissance efficaces. Le SL présente des délais de propagation mesurés de 7.6ns. Les résultats mesurés montrent le fonctionnement du circuit présenté sur la plage de fréquence de 1MHz à 130MHz. Le circuit fabriqué consomme 31.5pW de puissance statique et 3.4pJ d'énergie par transition à 1kHz, V[indice DDL] = 0.8V , V[indice DDH] = 3.0V, et une charge capacitive C[indice L] = 0.1pF. La consommation énergétique totale mesurée par rapport à la charge capacitive de 0.1 à 100nF est indiquée. Un autre nouveau décalage vers le bas est proposé pour être utilisé sur le côté bas des pilotes de portes. Ce circuit est également nécessaire dans la partie Rₓ du réseau de bus de données pour recevoir le signal haute tension du réseau et délivrer un signal de faible amplitude à la partie basse tension. L'une des principales contributions de ces travaux est la proposition d'un modèle de référence pour l'abaissement de niveau à puissance unique reconfigurable. Le circuit proposé pilote avec succès une gamme de charges capacitives allant de 10fF à 350pF. Le circuit présenté consomme des puissances statiques et dynamiques de 62.37pW et 108.9µW, respectivement, à partir d'une alimentation de 3.3V lorsqu'il fonctionne à 1MHz et pilote une charge capacitive de 10pF. Les résultats de la simulation post-layout montrent que les délais de propagation de chute et de montée dans les trois configurations sont respectivement de l'ordre de 0.54 à 26.5ns et de 11.2 à 117.2ns. La puce occupe une surface de 80µm × 100µm. En effet, les temps morts des côtés hauts et bas varient en raison de la différence de fonctionnement des commutateurs de puissance côté haut et côté bas, qui sont respectivement en commutation dure et douce. Par conséquent, un générateur de temps mort reconfigurable asymétrique doit être ajouté aux pilotes de portes traditionnelles pour obtenir une conversion efficace. Notamment, le temps mort asymétrique optimal pour les côtés hauts et bas des convertisseurs de puissance à base de Gan doit être fourni par un circuit de commande de grille reconfigurable pour obtenir une conception efficace. Le temps mort optimal pour les convertisseurs de puissance dépend de la topologie. Une autre contribution importante de ce travail est la dérivation d'une équation précise du temps mort optimal pour un convertisseur buck. Le générateur de temps mort asymétrique reconfigurable fabriqué sur mesure est connecté à un convertisseur buck pour valider le fonctionnement du circuit proposé et l'équation dérivée. De plus le rendement d'un convertisseur buck typique avec T[indice DLH] minimum et T[indice DHL] optimal (basé sur l'équation dérivée) à I[indice Load] = 25mA est amélioré de 12% par rapport à un convertisseur avec un temps mort fixe de T[indice DLH] = T[indice DHL] = 12ns.Power management systems require power converters to provide appropriate power conversion for various purposes. Class D power amplifiers, half and full bridges, class E power amplifiers, buck converters, and boost converters are different types of power converters. Power efficiency and density are two prominent specifications for designing a power converter. For example, in implantable devices, when power is harvested from the main source, buck or boost power converters are required to receive the power from the input and deliver clean power to different parts of the system. In charge stations of electric cars, new cell phones, neural stimulators, and so on, power is transmitted wirelessly, and Class E power amplifiers are developed to accomplish this task. In headphone or speaker driver applications, Class D power amplifiers are an excellent choice due to their great efficiency. In sensor interfaces, half and full bridges are the appropriate interfaces between the low- and high-power sides of systems. In automotive applications, the sensor interface receives the signal from the low-power side and transmits it to a network on the high-power side. In addition, the sensor interface must receive a signal from the high-power side and convert it down to the low-power side. All the above-summarized systems require a particular gate driver to be included in the circuits depending on the applications. The gate drivers generally consist of the level-up shifter, the level-down shifter, a buffer chain, an under-voltage lock-out circuit, a deadtime circuit, logic gates, the Schmitt trigger, and a bootstrap mechanism. These circuits are necessary to achieve the proper functionality of the power converter systems. A reconfigurable gate driver would support a wide range of power converters with variable input voltage V[subscript IN] and output current I[subscript Load]. The goal of this project is to intensively investigate the causes of different losses in power converters and then propose novel circuits and methodologies in the different circuits of gate drivers to achieve power conversion with high-power efficiency and density. We propose novel deadtime circuits, level-up shifter, and level-down shifter with new topologies that were fully characterized experimentally. Furthermore, the mathematical equation for optimum deadtimes for the high and low sides of a buck converter is derived and proven experimentally. The proposed custom integrated circuits and methodologies are validated with different power converters, such as half bridge and open loop buck converters, using off-the-shelf components to demonstrate their superiority over traditional solutions. The main contributions of this research have been presented in seven high prestigious conferences, three peer-reviewed articles, which have been published or submitted, and one invention disclosure. An important contribution of this research work is the proposal of a novel custom integrated CMOS active non-overlapping signal generator, which was fabricated using the 0.35−µm AMS technology and consumes 16.8mW from a 3.3−V supply voltage to appropriately drive the low and high sides of the half bridge to remove the shoot-through. The fabricated chip is validated experimentally with a half bridge, which was implemented with off-the-shelf components and driving a R-L load. Measurement results show a 40% reduction in the total loss of a 45 − V input 1 − MHz half bridge compared with the half bridge operation without our custom integrated circuit. The main circuit of high-side gate driver is the level-up shifter, which provides a signal with a large amplitude for the high-side power switch. A new level shifter structure with minimal propagation delay must be presented. We propose a novel level shifter topology for the high side of gate drivers to produce efficient power converters. The LS shows measured propagation delays of 7.6ns. The measured results demonstrate the operation of the presented circuit over the frequency range of 1MHz to 130MHz. The fabricated circuit consumes 31.5pW of static power and 3.4pJ of energy per transition at 1kHz, V[subscript DDL] = 0.8V , V[subscript DDH] = 3.0V , and capacitive load C[subscript L] = 0.1pF. The measured total power consumption versus the capacitive load from 0.1pF to 100nF is reported. Another new level-down shifter is proposed to be used on the low side of gate drivers. Another new level-down shifter is proposed to be used on the low side of gate drivers. This circuit is also required in the Rₓ part of the data bus network to receive the high-voltage signal from the network and deliver a signal with a low amplitude to the low-voltage part. An essential contribution of this work is the proposal of a single supply reconfigurable level-down shifter. The proposed circuit successfully drives a range of capacitive load from 10fF to 350pF. The presented circuit consumes static and dynamic powers of 62.37pW and 108.9µW, respectively, from a 3.3 − V supply when working at 1MHz and drives a 10pF capacitive load. The post-layout simulation results show that the fall and rise propagation delays in the three configurations are in the range of 0.54 − 26.5ns and 11.2 − 117.2ns, respectively. Its core occupies an area of 80µm × 100µm. Indeed, the deadtimes for the high and low sides vary due to the difference in the operation of the high- and low-side power switches, which are under hard and soft switching, respectively. Therefore, an asymmetric reconfigurable deadtime generator must be added to the traditional gate drivers to achieve efficient conversion. Notably, the optimal asymmetric deadtime for the high and low sides of GaN-based power converters must be provided by a reconfigurable gate driver to achieve efficient design. The optimum deadtime for power converters depends on the topology. Another important contribution of this work is the derivation of an accurate equation of optimum deadtime for a buck converter. The custom fabricated reconfigurable asymmetric deadtime generator is connected to a buck converter to validate the operation of the proposed circuit and the derived equation. The efficiency of a typical buck converter with minimum T[subscript DLH] and optimal T[subscript DHL] (based on the derived equation) at I[subscript Load] = 25mA is improved by 12% compared to a converter with a fixed deadtime of T[subscript DLH] = T[subscript DHL] = 12ns