A CMOS Digital Beamforming Receiver

As the demand for high speed communication is increasing, emerging wireless techniques seek to utilize unoccupied frequency ranges, such as the mm-wave range. Due to high path loss for higher carrier frequencies, beamforming is an essential technology for mm-wave communication. Compared to analog beamforming, digital beamforming provides multiple simultaneous beams without an SNR penalty, is more accurate, enables faster steering, and provides full access to each element. Despite these advantages, digital beamforming has been limited by high power consumption, large die area, and the need for large numbers of analog-to-digital converters. Furthermore, beam squinting errors and ADC non-linearity limit the use of large digital beamforming arrays. We address these limitations. First, we address the power and area challenge by combining Interleaved Bit Stream Processing (IL-BSP) with power and area efficient Continuous-Time Band-Pass Delta-Sigma Modulators (CTBPDSMs). Compared to conventional DSP, IL-BSP reduces both power and area by 80%. Furthermore, the new CTBPDSM architecture reduces ADC area by 67% and the energy per conversion by 43% compared to previous work. Second, we introduce the first integrated digital true-time-delay digital beamforming receiver to resolve the beam squinting. True-time-delay beamforming eliminates squinting, making it an ideal choice for large-array wide-bandwidth applications. Third, we present a new current-steering DAC architecture that provides a constant output impedance to improve ADC linearity. This significantly reduces distortion, leading to an SFDR improvement of 13.7 dB from the array. Finally, we provide analysis to show that the ADC power consumption of a digital beamformer is comparable to that of the ADC power for an analog beamformer. To summarize, we present a prototype phased array and a prototype timed array, both with 16 elements, 4 independent beams, a 1 GHz center frequency, and a 100 MHz bandwidth. Both the phased array and timed array achieve nearly ideal conventional and adaptive beam patterns, including beam tapering and adaptive nulling. With an 11.2 dB array gain, the phased array achieves a 58.5 dB SNDR over a 100 MHz bandwidth, while consuming 312 mW and occupying 0.22 mm2. The timed array achieves an EVM better than -37 dB for 5 MBd QAM-256 and QAM-512, occupies only 0.29 mm2, and consumes 453 mW.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147716/1/smjang_1.pd

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications

Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switchÂs speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulatorÂs power consumption is 302 mW from supply power of ± 1.65V

Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR

This paper presents the design and implementation of a fourth-order band-pass continuous-time modulator intended for the digitization of radio-frequency signals in softwaredefined- radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the forward path and a non-return-to-zero digital-to-analog converter with a finiteimpulse- response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65- nm CMOS, can digitise signals with up to 57-dB SNDR within a 40-MHz bandwidth, with an adaptive power dissipation of 16.7- to-22.8 mW and a programmable 1.2/2GHz clock rate1

Bandpass electromechanical sigma-delta modulator

Ph.DDOCTOR OF PHILOSOPH

High Performance Integrated Circuit Blocks for High-IF Wideband Receivers

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content

Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver

Low Power Continuous-time Bandpass Delta-Sigma Modulators.

Low power techniques for continuous-time bandpass delta-sigma modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW. Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators. The techniques introduced in this research help CTBPDSMs have good power efficiency compared with the other kinds of ADCs, and make the implement of a software-defined radio architecture easier which is appropriate for the future multiple standard radio receivers without a power penalty.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98001/1/hichae_1.pd