A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Challenges and Solutions for High Performance Analog Circuits with Robust Operation in Low Power Digital CMOS

In modern System-on-Chip products, analog circuits need to co-exist with digital circuits integrated on the same chip. This brings on a lot of challenges since analog circuits need to maintain their performance while being subjected to disturbances from the digital circuits. Device size scaling is driven by digital applications to reduce size and improve performance but also results in the need to reduce the supply voltage. Moreover, in some applications, digital circuits require a changing supply voltage to adapt performance to workloads. So it is further desirable to develop design solutions for analog circuits that can operate with a flexible supply voltage, which can be reduced well below 1V. In this thesis challenges and solutions for key high performance analog circuit functions are explored and demonstrated that operate robustly in a digital environment, function with flexible supply voltages or have a digital-like operation. A combined phase detector consisting of a phase-frequency detector and sub-sampling phase detector is proposed for phase-locked loops (PLLs). The phase-frequency function offers robust operation and the sub-sampling detector leads to low in-band phase noise. A 2.2GHz PLL with a combined phase detector was prototyped in a 65nm CMOS process, with an on-chip loop filter area of only 0.04mm². The experimental results show that the PLL with the combined phase detector is more robust to disturbances than a sub-sampling PLL, while still achieving a measured in-band phase noise of -122dBc/Hz which is comparable to the excellent noise performance of a sub-sampling PLL. A pulse-controlled common-mode feedback (CMFB) circuit is proposed for a 0.6V-1.2V supply-scalable fully-differential amplifier that was implemented in a low power/leakage 65nm CMOS technology. An integrator built with the amplifier occupies an active area of 0.01mm². When the supply is changed from 0.6V to 1.2V, the measured frequency response changes are small, demonstrating the flexible supply operation of the differential amplifier with the pulse-controlled CMFB. Next, models are developed to study the performance scaling of a continuous-time sigma-delta modulator (SDM) with a varying supply voltage. It is demonstrated that the loop filter and the quantizer exhibit different supply dependence. The loop noise performance becomes better at a higher supply thanks to larger signal swings and better signal-to-noise ratio, while the figure of merit determined by the quantization noise gets better at a lower supply voltage, thanks to the quantizer power dissipation reduction. The theoretical models were verified with simulations of a 0.6V-1.2V 2MHz continuous-time SDM design in a 65nm CMOS low power/leakage process. Finally, two design techniques are introduced that leverage the continued improvement of digital circuit blocks for the realization of analog functions. A voltage-controlled-ring-oscillator-based amplifier with zero compensation is proposed that internally uses a phase-domain representation of the analog signal. This provides a huge DC gain without significant penalties on the unity-gain bandwidth or area. With this amplifier a 4th-order 40-MHz active-UGB-RC filter was implemented that offers a wide bandwidth, superior linearity and small area. The filter prototype in a 55nm CMOS process has an active area of 0.07mm² and a power consumption of 7.8mW at 1.2V. The in-band IIP3 and out-of-band IIP3 are measured as 27.3dBm and 22.5dBm, respectively. A digital in-situ biasing technique is proposed to overcome the design challenges of conventional analog biasing circuits in an advanced CMOS process. A digital CMFB was simulated in a 65nm CMOS technology to demonstrate the advantages of this digital biasing scheme. Using time-based successive approximation conversion, the digital CMFB provides the desired analog output with a more robust operation and a smaller area, but without needing any stability compensation schemes like in conventional analog CMFBs. In summary, analog design techniques are continuously evolving to adapt to the integration with digital circuits on the same chip and are increasingly using digital-like blocks to realize analog functions in highly-integrated SOC chips. The signal representation in analog circuits is moving from traditional electrical signals such as voltage or current, to time and phase-domain representations. These changes make analog circuits more robust to voltage disturbances and supply variations. In addition to improved robustness, analog circuits based on timing signals benefit from the faster and smaller transistors offered by the continued feature scaling in CMOS technologies

A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization

A large-scale timing synchronization scheme for scalable phased arrays is presented. This approach utilizes a DLL co-designed with a subsequent 2.5GHz PLL. The DLL employs a low noise, fine/coarse delay tuning to reduce the in-band rms jitter to 323fs, an order of magnitude improvement over previous works at similar frequencies. The DLL was fabricated in a 65nm bulk CMOS process and was characterized from 27MHz to 270MHz. It consumes up to 3.3mW from a 1V power supply and has a small footprint of 0.036mm^2

Feedback methods for inductorless bandwidth extension and linearisation of post-amplifiers in optical receiver frontends

Optical communication is increasingly important in today's telecommunications. It is not only a key component in long-haul infrastructure, but is also being brought into new applications within the datacentre, at the circuit board and integrated circuit level, and in next generation mobile networks. This thesis proposes feedback tuning approaches in order to address two challenges within optical receiver analog frontend circuits: a) the dynamic response of a prior bandwidth extension technique; and b) linearity optimisation. To address dynamic response, we begin with an inductorless method of bandwidth extension using positive feedback loops. In a multi-stage post-amplifier with local positive feedback loops, we propose an approach which tunes each positive feedback gain separately, and demonstrate that this achieves better dynamic response and eye opening than the prior equal-feedback-gain approach. We additionally propose root-locus analysis as a means of characterising dynamic response, and suggest some design guidelines based on this analysis. To address linearity optimisation, we propose the use of an interleaving negative-feedback post-amplifier topology, previously proposed only for bandwidth extension. We investigate the relationship between the feedback gains and linearity and develop a design approach for linearity optimisation. We then designed and fabricated two 70 dB 6 GHz optical receiver circuits, making use of two different post-amplifiers, in order to compare different design approaches. We achieved a linearity of 0.08 dBVrms OIP3 (quasi-static) and a THD of 0.195\% at 1 GHz

Enhanced dynamic nuclear polarization via swept microwave frequency combs

Dynamic Nuclear Polarization (DNP) has enabled enormous gains in magnetic resonance signals and led to vastly accelerated NMR/MRI imaging and spectroscopy. Unlike conventional cw-techniques, DNP methods that exploit the full electron spectrum are appealing since they allow direct participation of all electrons in the hyperpolarization process. Such methods typically entail sweeps of microwave radiation over the broad electron linewidth to excite DNP, but are often inefficient because the sweeps, constrained by adiabaticity requirements, are slow. In this paper we develop a technique to overcome the DNP bottlenecks set by the slow sweeps, employing a swept microwave frequency comb that increases the effective number of polarization transfer events while respecting adiabaticity constraints. This allows a multiplicative gain in DNP enhancement, scaling with the number of comb frequencies and limited only by the hyperfine-mediated electron linewidth. We demonstrate the technique for the optical hyperpolarization of 13C nuclei in powdered microdiamonds at low fields, increasing the DNP enhancement from 30 to 100 measured with respect to the thermal signal at 7T. For low concentrations of broad linewidth electron radicals, e.g. TEMPO, these multiplicative gains could exceed an order of magnitude.Comment: Contains supplementary inf

Synchronising coherent networked radar using low-cost GPS-disciplined oscillators

This text evaluates the feasibility of synchronising coherent, pulsed-Doppler, networked, radars with carrier frequencies of a few gigahertz and moderate bandwidths of tens of megahertz across short baselines of a few kilometres using low-cost quartz GPSDOs based on one-way GPS time transfer. It further assesses the use of line-of-sight (LOS) phase compensation, where the direct sidelobe breakthrough is used as the phase reference, to improve the GPS-disciplined oscillator (GPSDO) synchronised bistatic Doppler performance. Coherent bistatic, multistatic, and networked radars require accurate time, frequency, and phase synchronisation. Global positioning system (GPS) synchronisation is precise, low-cost, passive and covert, and appears well-suited to synchronise networked radar. However, very few published examples exist. An imperfectly synchronised bistatic transmitter-receiver is modelled. Measures and plots are developed enabling the rapid selection of appropriate synchronisation technologies. Three low-cost, open, versatile, and extensible, quartz-based GPSDOs are designed and calibrated at zero-baselines. These GPSDOs are uniquely capable of acquiring phase-lock four times faster than conventional phase-locked loops (PLLs) and a new time synchronisation mechanism enables low-jitter sub-10 ns oneway GPS time synchronisation. In collaboration with University College London, UK, the 2.4 GHz coherent pulsed-Doppler networked radar, called NetRAD, is synchronised using the University of Cape Town developed GPSDOs. This resulted in the first published example of pulsed-Doppler phase synchronisation using GPS. A tri-static experiment is set up in Simon’s Bay, South Africa, with a maximum baseline of 2.3 km. The Roman Rock lighthouse was used as a static target to simultaneously assess the range, frequency, phase, and Doppler performance of the monostatic, bistatic, and LOS phase corrected bistatic returns. The real-world results compare well to that predicted by the earlier developed bistatic model and zero-baseline calibrations. GPS timing limits the radar bandwidth to less than 37.5 MHz when it is required to synchronise to within the range resolution. Low-cost quartz GPSDOs offer adequate frequency synchronisation to ensure a target radial velocity accuracy of better than 1 km/h and frequency drift of less than the Doppler resolution over integration periods of one second or less. LOS phase compensation, when used in combination with low-cost GPSDOs, results in near monostatic pulsed-Doppler performance with a subclutter visibility improvement of about 30 dB

RF Amplification and Filtering Techniques for Cellular Receivers

The usage of various wireless standards, such as Bluetooth, Wi-Fi, GPS, and 4G/5G cellular, has been continually increasing. In order to utilize the frequency bands efficiently and to support new communication standards with lower power consumption, lower occupied volume and at reduced costs, multimode transceivers, software defined radios (SDRs), cognitive radios, etc., have been actively investigated. Broadband behavior of a wireless receiver is typically defined by its front-end low-noise amplifier (LNA), whose design must consider trade-offs between input matching, noise figure (NF), gain, bandwidth, linearity, and voltage headroom in a given process technology. Moreover, monolithic RF wireless receivers have been trending toward high intermediatefrequency (IF) or superhetrodyne radios thanks to recent breakthroughs in silicon integration of band-pass channel-select filters. The main motivation is to avoid the common issues in the currently predominant zero/low-IF receivers, such as poor 2nd-order nonlinearity, sensitivity to 1/f (i.e. flicker) noise and time-variant dc offsets, especially in the fine CMOS technology. To avoid interferers and blockers at the susceptible image frequencies that the high-IF entails, band-pass filters (BPF) with high quality (Q) factor components for sharp transfer-function transition characteristics are now required. In addition, integrated low-pass filters (LPF) with strong rejection of out-of-band frequency components are essential building blocks in a variety of applications, such as telecommunications, video signal processing, anti-aliasing filtering, etc. Attention is drawn toward structures featuring low noise, small area, high in-/out-of-band linearity performance, and low-power consumption. This thesis comprises three main parts. In the first part (Chapters 2 and 3), we focus on the design and implementation of several innovative wideband low-noise (transconductance) amplifiers [LN(T)A] for wireless cellular applications. In the first design, we introduce new approaches to reduce the noise figure of the noise-cancellation LNAs without sacrificing the power consumption budget, which leads to NF of 2 dB without adding extra power consumption. The proposed LNAs also have the capability to be used in current-mode receivers, especially in discrete-time receivers, as in the form of low noise transconductance amplifier (LNTA). In the second design, two different two-fold noise cancellation approaches are proposed, which not only improve the noise performance of the design, but also achieve high linearity (IIP3=+4.25 dBm). The proposed LN(T)As are implemented in TSMC 28-nm LP CMOS technology to prove that they are suitable for applications such as sub-6 GHz 5G receivers. The second objective of this dissertation research is to invent a novel method of band-pass filtering, which leads to achieving very sharp and selective band-pass filtering with high linearity and low input referred (IRN) noise (Chapter 4). This technique improves the noise and linearity performance without adding extra clock phases. Hence, the duty cycle of the clock phases stays constant, despite the sophisticated improvements. Moreover, due to its sharp filtering, it can filter out high blockers of near channels and can increase the receiver’s blocker tolerance. With the same total capacitor size and clock duty cycle as in a 1st-order complex charge-sharing band-pass filter (CS BPF), the proposed design achieves 20 dB better out-of-band filtering compared to the prior-art 1st-order CS BPF and 10 dB better out-of-band filtering compared to the conventional 2nd-order C-CS BPF. Finally, the stop-band rejection of the discrete-time infinite-impulse response (IIR) lowpass filter is improved by applying a novel technique to enhance the anti-aliasing filtering (Chapter 5). The aim is to introduce a 4th-order charge rotating (CR) discrete-time (DT) LPF, which achieves the record of stop-band rejection of 120 dB by using a novel pseudolinear interpolation technique while keeping the sampling frequency and the capacitor values constant

A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization

A large-scale timing synchronization scheme for scalable phased arrays is presented. This approach utilizes a DLL co-designed with a subsequent 2.5GHz PLL. The DLL employs a low noise, fine/coarse delay tuning to reduce the in-band rms jitter to 323fs, an order of magnitude improvement over previous works at similar frequencies. The DLL was fabricated in a 65nm bulk CMOS process and was characterized from 27MHz to 270MHz. It consumes up to 3.3mW from a 1V power supply and has a small footprint of 0.036mm^2

Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors

University of Minnesota Ph.D. dissertation.November 2016. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); x, 137 pages.Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V