Design and implementation of 4 bit binary weighted current steering DAC

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation

An Ultra Low Power Digital to Analog Converter Optimized for Small Format LCD Applications

Liquid crystal displays (LCDs) for mobile applications present a unique design challenge. These small format displays can be found primarily in cell phones and PDAs which are devices that have particularly stringent power requirements. At the same time, the displays are increasing in resolution with every generation. This is creating demand for new LCD display technologies. The predominant amorphous thin film transistor technology is no longer feasible in the new high resolution small format screens due to the fact that the displays require too many connections to the driver and the aperture ratios do not allow high density displays. New technologies such as low temperature polysilicon (LTPS) displays continue to shrink in size and increase in resolution. LTPS technology enables the display manufacturer to create relatively high quality transistors on the glass. This allows for a display architecture which integrates the gate driver on the glass. Newer LTPS LCDs also enable a high level of multiplexing the sources lines on the glass which allows for a much simpler connection to the display driver chip. The electronic drivers for these display applications must adhere to strict power and area budgets. This work describes a low-power, area efficient, scalable, digital-to-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. The display driver is based on a twelve channel, 9-bit DAC driver. This architecture, suitable for % VGA resolution displays, exhibited a 2 MSPS conversion rate, less than 300 pW power dissipation per channel using a 5 V supply, and a die area of 0.042 mm per DAC. A new performance standard is set for DAC display drivers in joules per bit areal density

Image capture using integrated 3D SoftChip technology

Mobile multimedia communication has rapidly become a significant area of research and development. The processing requirements for the capture, conversion, compression, decompression, enhancement, display, etc. of high quality multimedia content places heavy demands even on current ULSI (ultra large scale integration) systems, particularly for mobile applications where area and power are primary considerations. The system presented is designed as a vertically integrated (3D) system comprising two distinct layers bonded together using indium bump technology. The top layer is a CMOS imaging array containing analog-to-digital converters, and a buffer memory. The bottom layer takes the form of a configurable array processor (CAP), a highly parallel array of soft programmable processors capable of carrying out complex processing tasks directly on data stored in the top plane. Until recently, the dominant format of data in imaging devices has been analog. The analog photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. In the proposed system, an array of analog-to-digital converters is distributed, so that a one-bit cell is associated with one sensor. The analog-to-digital converters are algorithmic current-mode converters. Eight such cells are cascaded to form an 8-bit converter. Additionally, each photosensor is equipped with a current memory cell, and multiple conversions are performed with scaled values of the photocurrent for colour processing

Development of an X-ray detection system based on polymer-based scintillator composites

Dissertação de mestrado em Engenharia Eletrónica Industrial e de ComputadoresNowadays, radiation processing techniques are used in many fields and are undergoing fast developments. The demand for improving spatial resolution and to obtain more clear and accurate images, while reducing the radiation doses, have led to the replacement of the traditional techniques based on X-ray films processing by digital processing techniques, that combine high efficiency electronic sensors with computing algorithms. However, these current techniques and radiation detection methods face severe limitations and high costs when large areas or flexible applications are involved. In this work an X-ray detection system was developed, with the aim of presenting an innovative solution, efficient, flexible, and capable of being produced in a large area and at a low cost. To achieve these objectives, a Styrene-Ethylene/Butadiene-Styrene (SEBS) polymer films were prepared, containing scintillator nanoparticles, Gd2O3:Eu3+, that are responsible for converting X-rays into visible light. These materials present unique characteristics like flexibility, stretchability and easy and low cost production. It was also developed a compact electronic circuit responsible for acquiring and processing the visible light produced by the scintillator material. This circuit is based on a photodetector matrix and auxiliary components that have to obtain visible light values, multiplex the matrix sensors and communicate the results to a microcontroller. Thereafter, a firmware to the microcontroller was implemented to control the whole system, from sensors acquisition to sending the data through serial communication to a user interface. The results are displayed and presented to the user in a clear and organized way, allowing the user to make an easy and direct analysis. Finally, the system was subject to tests according to a previously defined experimental methodology. In these experiments, the system revealed a fluid, solid and clean performance with room for optimization, improvements and adaptation to new and innovative applications.Actualmente, as técnicas de processamento de radiação são usadas em muitas áreas de investigação e aplicação, ao mesmo tempo que sofrem uma constante e rápida evolução. A necessidade de melhorar a resolução e obter imagens mais claras e precisas, ao mesmo tempo que é reduzida a quantidade de radiação, levaram a que as técnicas tradicionais baseadas no processamento de películas radiográficas fossem sendo substituídas por técnicas de processamento digital, que aliam sensores electrónicos de alta eficiência com programação algorítmica. No entanto, estas técnicas e métodos de detecção de radiação actuais enfrentam duras limitações e elevados custos quando é pretendida a produção de grandes áreas de detecção ou a integração em aplicações flexíveis. Nesta dissertação é desenvolvido um sistema de detecção de raio-X com o objectivo de apresentar uma solução inovadora, que seja eficiente, flexível e capaz de ser produzida em grandes áreas e a baixo custo. Para cumprir estes objectivos, foi preparada uma matriz polimérica de StyreneEthylene/Butadiene-Styrene (SEBS) contendo concentrações de nanopartículas cintiladoras, Gd2O3:Eu 3+, responsáveis por converter os raios-X em luz visível. Este material cintilador apresenta características ímpares, como flexibilidade, extensibilidade, baixo custo e fácil produção e replicação. Foi também desenvolvido um circuito electrónico de reduzidas dimensões, responsável por adquirir e processar a luz visível produzida pelo cintilador. Este circuito foi implementado com base numa matriz de fotodetectores e componentes electrónicos auxiliares que têm como função obter os valores de luz visível, efectuar a multiplexagem dos sensores da matriz, e enviar os dados para o microcontrolador. Posteriormente foi desenvolvido um firmware para o microcontrolador capaz de efectuar o controlo de todo o sistema, desde a aquisição dos sensores até ao envio dos dados através de comunicação série para uma interface com o utilizador. Os resultados são apresentados ao utilizador de uma forma clara e organizada, permitindo uma análise directa e facilitada destes. Por fim, o sistema foi sujeito a testes de acordo com uma metodologia previamente definida. Nestes testes, o sistema revelou um desempenho fluído, sólido e direto, havendo espaço para a sua optimização, melhoramento e adaptação para novas aplicações

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 ??m complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.ope

Infrastructure for Detector Research and Development towards the International Linear Collider

The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation

Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling

In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort, enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40-nm testchip, graceful degradation of 0.3bit/100mV is achieved when V_DD is over-scaled down to 0.8V, and 1.4bit/100mV when further scaled down to 0.6V. The proposed DAC enables dynamic power-resolution tradeoff with 3X (2X) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40nm consumes 55µW at 27kS/s (9.1µW at 13.5kS/s) at a compact area of 500µm^2 and low voltage of 0.55V