Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems

This paper presents an energy-efficient, duty-cycled, and spinning excitation bridge-to-digital converter (BDC) designed for implantable pressure sensing systems. The circuit provides the measure of the pulmonary artery pressure that is particularly relevant for the monitoring of heart failure and pulmonary hypertension patients. The BDC is made of a piezoresistive pressure sensor and a readout integrated circuit (IC) that comprises an instrumentation amplifier (IA) followed by an analog-to-digital converter (ADC). The proposed design spins both the bridge excitation and the ADC’s sampling input voltages simultaneously and exploits duty cycling to reduce the static power consumption of the bridge sensor and IA while cancelling the IA’s offset and 1/f noise at the same time. The readout IC has been designed and fabricated in a standard 180-nm CMOS process and achieves 8.4 effective number of bits (ENOB) at 1 kHz sampling rate while drawing 0.53 µA current from a 1.2 V supply. The BDC, built with the readout IC and a differential pressure sensor having 5 kΩ bridge resistances, achieves 0.44 mmHg resolution in a 270 mmHg pressure range at 1 ms conversion time. The current consumption of the bridge sensor by employing duty cycling is reduced by 99.8% thus becoming 0.39 µA from a 1.2 V supply. The total conversion energy of the pressure sensing system is 1.1 nJ, and achieves a figure-of-merit (FoM) of 3.3 pJ/conversion, which both represent the state of the art

A 5.5 μW 42nV/√Hz Chopper stabilized Amplifier for Biomedical Application with Input Impedance Enhancement

The continuous real-time monitoring of diverse physical parameters using biosignals like ECG and EEG requires the biomedical sensors. Such sensor consists of analog frontend unit for which low noise and low power Operational transconductance amplifier (OTA) is essential. In this paper, the novel chopper-stabilized bio-potential amplifier is proposed. The chopper stabilization technique is used to reduce the offset and flicker noise. Further, the OTA is likewise comprised of a method to enhance the input impedance without consuming more power. Also, the ripple reduction technique is used at the output branch of the OTA. The designed amplifier consumes 5.5 μW power with the mid-band gain of 40dB. The pass-band for the designed amplifier is 0.1Hz to 1KHz. The input impedance is likewise boosted with the proposed method. The noise is 42 nV/√Hz with CMRR of 82 dB. All simulations are carried out in 180nm parameters

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

12.8 kHz Energy-Efficient Read-Out IC for High Precision Bridge Sensor Sensing System

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 김수환.In the thesis, a high energy-efficient read-out integrated circuit (read-out IC) for a high-precision bridge sensor sensing system is proposed. A low-noise capacitively-coupled chopper instrumentation amplifier (CCIA) followed by a high-resolution incremental discrete-time delta-sigma modulator (DTΔΣΜ) analog-to-digital converter (ADC) is implemented. To increase energy-efficiency, CCIA is chosen, which has the highest energy-efficiency among IA types. CCIA has a programmable gain of 1 to 128 that can amplify the small output of the bridge sensor. Impedance boosting loop (IBL) is applied to compensate for the low input impedance, which is a disadvantage of a CCIA. Also, the sensor offset cancellation technique was applied to CCIA to eliminate the offset resulting from the resistance mismatch of the bridge sensor, and the bridge sensor offset from -350 mV to 350 mV can be eliminated. In addition, the output data rate of the read-out IC is designed to be 12.8 kHz to quickly capture data and to reduce the power consumption of the sensor by turning off the sensor and read-out IC for the rest of the time. Generally, bridge sensor system is much slower than 12.8 kHz. To suppress 1/f noise, system level chopping and correlated double sampling (CDS) techniques are used. Implemented in a standard 0.13-μm CMOS process, the ROIC’s effective resolution is 17.0 bits at gain 1 and that of 14.6 bits at gain 128. The analog part draws the average current of 139.4 μA from 3-V supply, and 60.2 μA from a 1.8 V supply.본 논문에서는 고정밀 브리지 센서 센싱 시스템을 위한 에너지 효율이 높은 Read-out Integrated Circuit (read-out IC)를 제안한다. 저 잡음 Capacitively-Coupled Instrumentation Amplifier (CCIA)에 이은 고해상도 Discrete-time Delta-Sigma 변조기(DTΔΣΜ) 아날로그-디지털 변환기(ADC)를 구현하였다. 에너지 효율을 높이기 위해 IA 유형 중 에너지 효율이 가장 높은 CCIA를 선택하였다. CCIA는 브리지 센서의 작은 출력을 증폭할 수 있는 1 에서 128의 프로그래밍 가능한 전압 이득을 가진다. CCIA의 단점인 낮은 입력 임피던스를 보상하기 위해 Impedance Boosting Loop (IBL)을 적용하였다. 또한 CCIA에 센서 오프셋 제거 기술을 적용하여 브리지 센서의 저항 미스매치로 인한 오프셋을 제거 기능을 탑재하였으며 -350mV에서 350mV까지 브리지 센서 오프셋을 제거할 수 있다. Read-out IC의 출력 데이터 전송률은 12.8kHz로 설계하여 데이터를 빠르게 채고 나머지 시간 동안 센서와 read-out IC를 꺼서 센서의 전력 소비를 줄일 수 있도록 설계하였다. 일반적으로 브리지 센서 시스템은 12.8kHz보다 느리기 때문에 이것이 가능하다. 하지만, 일반적인 CCIA는 입력 임피던스 때문에 빠른 속도에서 설계가 불가능하다. 이를 해결하기 위해 demodulate 차핑을 앰프 내부가 아닌 시스템 차핑을 이용해 해결하였다. 1/f 노이즈를 억제하기 위해 시스템 레벨 차핑 및 상관 이중 샘플링(CDS) 기술이 사용되었다. 0.13μm CMOS 공정에서 구현된 read-out IC의 Effective Resolution (ER)은 전압 이득 1에서 17.0비트이고 전압 이득 128에서 14.6비트를 달성하였다. 아날로그 회로는 3 V 전원에서 139.4μA의 평균 전류를, 디지털 회로는 1.8 V 전원에서 60.2μA의 평균 전류를 사용한다.CHAPTER 1 INTRODUCTION 1 1.1 SMART DEVICES 1 1.2 SMART SENSOR SYSTEMS 4 1.3 WHEATSTONE BRIDGE SENSOR 5 1.4 MOTIVATION 8 1.5 PREVIOUS WORKS 10 1.6 INTRODUCTION OF THE PROPOSED SYSTEM 14 1.7 THESIS ORGANIZATION 16 CHAPTER 2 SYSTEM OVERVIEW 17 2.1 SYSTEM ARCHITECTURE 17 CHAPTER 3 IMPLEMENTATION OF THE CCIA 19 3.1 CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER 19 3.2 IMPEDANCE BOOSTING 22 3.3 SENSOR OFFSET CANCELLATION 25 3.4 AMPLIFIER OFFSET CANCELLATION 29 3.5 AMPLIFIER IMPLEMENTATION 32 3.6 IMPLEMENTATION OF THE CCIA 35 CHAPTER 4 INCREMENTAL ΔΣ ADC 37 4.1 INTRODUCTION OF INCREMENTAL ΔΣ ADC 37 4.2 IMPLEMENTATION OF INCREMENTAL ΔΣ MODULATOR 40 CHAPTER 5 SYSTEM-LEVEL DESIGN 43 5.1 DIGITAL FILTER 43 5.2 SYSTEM-LEVEL CHOPPING & TIMING 46 CHAPTER 5 MEASUREMENT RESULTS 48 6.1 MEASUREMENT SUMMARY 48 6.2 LINEARITY & NOISE MEASUREMENT 51 6.3 SENSOR OFFSET CANCELLATION MEASUREMENT 57 6.4 INPUT IMPEDANCE MEASUREMENT 59 6.5 TEMPERATURE VARIATION MEASUREMENT 63 6.6 PERFORMANCE SUMMARY 66 CHAPTER 7 CONCLUSION 68 APPENDIX A. 69 ENERGY-EFFICIENT READ-OUT IC FOR HIGH-PRECISION DC MEASUREMENT SYSTEM WITH IA POWER REDUCTION TECHNIQUE 69 BIBLIOGRAPHY 83 한글초록 87박

Low-Noise Energy-Efficient Sensor Interface Circuits

Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone. Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy. An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures. Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd

Recent trends in low-frequency noise reduction techniques for integrated circuits

This paper presents the two main circuit techniques, namely autozeroing (AZ) and chopper stabilization (CS), that are used to reduce the 1/f noise and offset in amplifiers typically used in sensor electronics interfaces. After recalling their main properties, it looks into recent trends in circuit noise reduction techniques. First, the correlated multiple sampling (CMS) technique is presented as a generalization of AZ and correlated double sampling (CDS). Introduced in CMOS image sensors (CIS), it combines noise averaging and canceling and allows to further reduce the 1/f noise, but, like AZ, it is also ultimately limited by the aliasing of the broadband white noise. Another technique combining noise canceling and CS in a transimpedance amplifier (TIA) for bio-sensors is presented. It allows to maintain a low input impedance required by the TIA, while reducing the noise of the main transimpedance stage. CS is then used to cancel the noise of the following stages

Amplificador de Instrumentação de Baixa Potência em Tecnologia CMOS para um Sistema Integrado de Aquisição de Sinal com Sensores MEMS.

Esta dissertação apresenta o estudo de um amplificador de instrumentação integrado de Acomplamento Capacitivo (CCIA) para um analog front-end (AFE), otimizado para extrair sinais de um sensor tipo MEMS de elevada impedância. Este amplificador destina-se à integração num sistema AFE, implementado em tecnologia CMOS de 130 nm, do qual consiste num amplificador de instrumentação, um filtro passa-banda de condensadores comutados, e um conversor analógico digital do tipo sigma − delta. O amplificador de instrumentação é capaz de operar a tensões de alimentação inferiores a 1 V, com uma largura de banda (BW) até 10 kHz Visando a redução do ruido flícker, é utilizado uma técnica de modulação chopper, a qual acarreta uma consequente degradação da impedância de entrada. Todavia, esta é compensada por efeito de uma malha de realimentação positiva. Este amplificador de baixo ruído é constituído por um andar de entrada folded cascode, que recorre a uma técnica de distribuição de corrente para a diminuição de potência dissipada. Para além deste bloco de entrada, o circuito incluí um segundo andar common-drain e um andar de saída common-source. Para uma tensão de alimentação de 1 V, o amplificador de instrumentação apresenta uma potência total consumida de 2.6 µW, uma impedância de entrada superior a 1 GΩ, e um SNR máximo de 107 dB. O ganho em malha aberta é de 87 dB, com um GBW de 583.4 kHz. O ruído referente à entrada obtido é de 4.6 nVrms, com um valor NEF resultante de 4. O CMRR e PSRR obtidos são superiores a 97 dB e 66 dB, respectivamente, com uma área total ocupada de 0.06mm2.This dissertation presents the design of a low-noise capacitively-coupled instrumentation amplifier for an analog front-end (AFE) optimized for the extraction of signals from a high impedance MEMS sensor. This amplifier is part of an AFE which is implemented in a standard 130 nm bulk CMOS technology. Beside the high-impedance input amplifier, the AFE includes a programmable switch-capacitor bandpass filter and a sigma-delta modulator. The instrumentation amplifier is capable to operate with a sub-1 V power supply at a 10 kHz bandwidth. A chopper modulation technique is implemented to further reduce the flicker noise, with a positive feedback network, compensating the resulting low input impedance. The low-noise amplifier consists of a differential input pair folded cascode, using a current splitting technique to decrease the power consumption, with a common-drain configuration and a common source output stage. For a power supply of 1 V, the instrumentation amplifier achieves a total power consumption of 2.6 µW, with an equivalent input impedance greater then 1 GΩ and a maximum SNR of 107 dB. The open loop gain is 87 dB with a GBW of 584 kHz. The measured input referred noise is 4.6 µVrms, with a NEF value of 4. The minimum CMRR of the amplifier is 97 dB and the PSRR minus is 66 dB. The total area occupied is 0.06mm2

Low Power Bio-potential Amplifier (for EEG)

The size and dependency on power supply of current biopotential data acquisition systems prohibit continuous monitoring of biopotential signals through battery powered devices. As the interest in continuous monitoring of EEG increases for healthcare and research purposes such as seizure detection, there is an increasing need to bring down the power consumption on the biopotential amplifier (BPA). BPA is one of the most power consuming components in the biopotential data acquisition system. In this FYP, we will develop a method to improve the existing BPA using MIMOS 0.35um process technology through implementation of various low power flicker noise cancelation techniques. Techniques used include low impedance node chopping and non-overlapping demodulation chopping. The scope of this FYP is focusing on design and simulation on Cadence software in circuit level implementation. This work provides insights as well as a starting point in lowering the power consumption of bio-potential data acquisition system. This will help to enable battery power system for continuous monitoring of EEG signals in the future. This final report discusses on both the literature review, background of the projects and methodology as well as the outcome of the work. The report is concluded by suggesting future works that can be carried out in this final year project (FYP)