Design of Power Efficient and High Slew Rate Class AB OPAMP

The paper deals with aim to design an OPAMP of Class AB to achieve high power efficiency and slew rate. To have high slew rate the focus of the proposed work as high slew rate contributes to the fast and dynamic output response. Power efficiency is driving factor from MOORE’S law. A Push pull OPAMP with current replicating branch is used to achieve symmetrical wave with high slew rate. Adaptive biasing is another technique employed to increase the slew rate. According to the Moore’s law, increase in power takes place in adaptive biasing due to increase in transistors, but the proposed circuit is best tradeoff between slew rate and power efficient factors. The existing work could only increase the slew rate by 4 to 5 times, but our proposed work increases it even further compared to the existing work, at the same time it results in decrease of power. In this work we are combining two techniques, namely adaptive biasing and current replicating branch which combine to result in better slew rate without increase in power. The proposed work is implemented with Cadence Virtuoso tool

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007