비디오 클럭 주파수 보상 구조를 이용한 디스플레이포트 수신단 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 정덕균.This thesis presents the design of DisplayPort receiver which is a high speed digital display interface replacing existing interfaces such as DVI, HDMI, LVDS and so on. The two prototype chips are fabricated, one is a 5.4/2.7/1.62-Gb/s multi-rate DisplayPort receiver and the other is a 2.7/1.62-Gb/s multi-rate Embedded DisplayPort (eDP) receiver for an intra-panel display interface. The first receiver which is designed to support the external box-to-box display connection provides up to 4K resolution (4096×2160) with the maximum data rate of 21.6 Gb/s when 4 lanes are all used. The second one aims to connect internal chip-to-chip connection such as graphic processors to display panels in notebooks or tablet PCs. It supports the maximum data rate of 10.8 Gb/s with 4-lane operation which is able to provide the resolution of WQXGA (2560×1600). Since there is no dedicated clock channel, it must contain clock and data recovery (CDR) circuit to extract the link clock from the data stream. All-Digital CDR (ADCDR) is adopted for area efficiency and better performances of the multi-rate operation. The link rate is fixed but the video clock frequency range is fairly wide for supporting all display resolutions and frame rates. Thus, the wide range video clock frequency synthesizer is essential for reconstructing the transmitted video data. A source device starts link training before transmitting video data to recover the clock and establish the link. When the loss of synchronization between the source device and the sink device happens, it usually restarts the link training and try to re-establish the link. Since link training spends several milliseconds for initializing, the video image is not displayed properly in the sink device during this interval. The proposed clock recovery scheme can significantly shorten the time to recover from the link failure with the ADCDR topology. Once the link is established after link training, the ADCDR memorizes the DCO codes of the synchronization state and when the loss of synchronization happens, it restores the previous DCO code so that the clock is quickly recovered from the failure state without the link re-training. The direct all-digital frequency synthesizer is proposed to generate the cycle-accurate video clock frequency. The video clock frequency has wide range to cover all display formats and is determined by the division ratio of large M and N values. The proposed frequency synthesizer using a programmable integer divider and a multi-phase switching fractional divider with the delta-sigma modulation exhibits better performances and reduces the design complexity operating with the existing clock from the ADCDR circuit. In asynchronous clock system, the transmitted M value which changes over time is measured by using a counter running with the long reference period (N cycles) and updated once per blank period. Thus, the transmitted M is not accurate due to its low update rate, transport latency and quantization error. The proposed frequency error compensation scheme resolves these problems by monitoring the status of FIFO between the clock domains. The first prototype chip is fabricated in a 65-nm CMOS process and the physical layer occupies 1.39 mm2 and the estimated area of the link layer is 2.26 mm2. The physical layer dissipates 86/101/116 mW at 1.62/2.7/5.4 Gb/s data rate with all 4-lane operation. The power consumption of the link layer is 107/145/167 mW at 1.62/2.7/5.4 Gb/s. The second prototype chip, fabricated in a 0.13μm CMOS process, presents the physical layer area of 1.59 mm2 and the link layer area of 3.01 mm2. The physical layer dissipates 21 mW at 1.62 Gb/s and 29 mW at 2.7 Gb/s with 2-lane operation. The power consumption of the link layer is 31 mW at 1.62 Gb/s and 41 mW at 2.7 Gb/s with 2-lane operation. The core area of the video clock synthesizer occupies 0.04 mm2 and the power dissipation is 5.5 mW at a low bit rate and 9.1 mW at a high bit rate. The output frequency range is 25 to 330 MHz.ABSTRACT I CONTENTS IV LIST OF FIGURES VII LIST OF TABLES XII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 MOTIVATION 4 1.3 THESIS ORGANIZATION 12 CHAPTER 2 DIGITAL DISPLAY INTERFACE 13 2.1 OVERVIEW 13 2.2 DISPLAYPORT INTERFACE CHARACTERISTICS 18 2.2.1 DISPLAYPORT VERSION 1.2 18 2.2.2 EMBEDDED DISPLAYPORT VERSION 1.2 21 2.3 DISPLAYPORT INTERFACE ARCHITECTURE 23 2.3.1 LAYERED ARCHITECTURE 23 2.3.2 MAIN STREAM PROTOCOL 27 2.3.3 INITIALIZATION AND LINK TRAINING 30 2.3.3 VIDEO STREAM CLOCK RECOVERY 35 CHAPTER 3 DESIGN OF DISPLAYPORT RECEIVER 39 3.1 OVERVIEW 39 3.2 PHYSICAL LAYER 43 3.3 LINK LAYER 55 3.3.1 OVERALL ARCHITECTURE 55 3.3.2 AUX CHANNEL 58 3.3.3 VIDEO TIMING GENERATION 61 3.3.4 CONTENT PROTECTION 63 3.3.5 AUDIO TRANSMISSION 66 3.4 EXPERIMENTAL RESULTS 68 CHAPTER 4 DESIGN OF EMBEDDED DISPLAYPORT RECEIVER 81 4.1 OVERVIEW 81 4.2 PHYSICAL LAYER 84 4.3 LINK LAYER 88 4.3.1 OVERALL ARCHITECTURE 88 4.3.2 MAIN LINK STREAM 90 4.3.3 CONTENT PROTECTION 93 4.4 PROPOSED CLOCK RECOVERY SCHEME 94 4.5 EXPERIMENTAL RESULTS 100 CHAPTER 5 PROPOSED VIDEO CLOCK SYNTHESIZER AND FREQUENCY CONTROL SCHEME 113 5.1 MOTIVATION 113 5.2 PROPOSED VIDEO CLOCK SYNTHESIZER 115 5.3 BUILDING BLOCKS 121 5.4 FREQUENCY ERROR COMPENSATION 126 5.5 EXPERIMENTAL RESULTS 131 CHAPTER 6 CONCLUSION 138 BIBLIOGRAPHY 141 초 록 152Docto

RF MEMS reference oscillators platform for wireless communications

A complete platform for RF MEMS reference oscillator is built to replace bulky quartz from mobile devices, thus reducing size and cost. The design targets LTE transceivers. A low phase noise 76.8 MHz reference oscillator is designed using material temperature compensated AlN-on-silicon resonator. The thesis proposes a system combining piezoelectric resonator with low loading CMOS cross coupled series resonance oscillator to reach state-of-the-art LTE phase noise specifications. The designed resonator is a two port fundamental width extensional mode resonator. The resonator characterized by high unloaded quality factor in vacuum is designed with low temperature coefficient of frequency (TCF) using as compensation material which enhances the TCF from - 3000 ppm to 105 ppm across temperature ranges of -40˚C to 85˚C. By using a series resonant CMOS oscillator, phase noise of -123 dBc/Hz at 1 kHz, and -162 dBc/Hz at 1MHz offset is achieved. The oscillator’s integrated RMS jitter is 106 fs (10 kHz–20 MHz), consuming 850 μA, with startup time is 250μs, achieving a Figure-of-merit (FOM) of 216 dB. Electronic frequency compensation is presented to further enhance the frequency stability of the oscillator. Initial frequency offset of 8000 ppm and temperature drift errors are combined and further addressed electronically. A simple digital compensation circuitry generates a compensation word as an input to 21 bit MASH 1 -1-1 sigma delta modulator incorporated in RF LTE fractional N-PLL for frequency compensation. Temperature is sensed using low power BJT band-gap front end circuitry with 12 bit temperature to digital converter characterized by a resolution of 0.075˚C. The smart temperature sensor consumes only 4.6 μA. 700 MHz band LTE signal proved to have the stringent phase noise and frequency resolution specifications among all LTE bands. For this band, the achieved jitter value is 1.29 ps and the output frequency stability is 0.5 ppm over temperature ranges from -40˚C to 85˚C. The system is built on 32nm CMOS technology using 1.8V IO device

Clock Generation Design for Continuous-Time Sigma-Delta Analog-To-Digital Converter in Communication Systems

Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (ΣΔ) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass ΣΔ which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system. Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (ΣΔ) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption. Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz. Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits

The Design of Low Power Ultra-Wideband Transceiver

Ph.DDOCTOR OF PHILOSOPH

CMOS ASIC Design of Multi-frequency Multi-constellation GNSS Front-ends

With the emergence of the new global navigation satellite systems (GNSSs) such as Galileo, COMPASS and GLONASS, the US Global Positioning System (GPS) has new competitors. This multiplicity of constellations will offer new services and a much better satellite coverage. Public regulated service (PRS) is one of these new services that Galileo, the first global positioning service under civilian control, will offers. The PRS is a proprietary encrypted navigation designed to be more reliable and robust against jamming and provides premium quality in terms of position and timing and continuity of service, but it requires the use of FEs with extended capabilities. The project that this thesis starts from, aims to develop a dual frequency (E1 and E6) PRS receiver with a focus on a solution for professional applications that combines affordability and robustness. To limit the production cost, the choice of a monolithic design in a multi-purpose 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology have been selected, and to reduce the susceptibility to interference, the targeted receiver is composed of two independent FEs. The first ASIC described here is such FEs bundle. Each FE is composed of a radio frequency (RF) chain that includes a low-noise amplifier (LNA), a quadrature mixer, a frequency synthesizer (FS), two intermediate frequency (IF) filters, two variable-gain amplifiers (VGAs) and two 6-bit flash analog-to-digital converters (ADCs). Each have an IF bandwidth of 50 MHz to accommodate the wide-band PRS signals. The FE achieves a 30 dB of dynamic gain control at each channel. The complete receivers occupies a die area of 11.5 mm2 while consuming 115 mW from a supply of a 1.8 V. The second ASIC that targets civilian applications, is a reconfigurable single-channel FE that permits to exploit the interoperability among GNSSs. The FE can operate in two modes: a ¿narrow-band mode¿, dedicated to Beidou-B1 with an IF bandwidth of 8 MHz, and a ¿wide-band mode¿ with an IF bandwidth of 23 MHz, which can accommodate simultaneous reception of Beidou-B1/GPS-L1/Galileo-E1. These two modes consumes respectively 22.85 mA and 28.45 mA from a 1.8 V supply. Developed with the best linearity in mind, the FE shows very good linearity with an input-referred 1 dB compression point (IP1dB) of better than -27.6 dBm. The FE gain is stepwise flexible from 39 dB and to a maximum of 58 dB. The complete FE occupies a die area of only 2.6 mm2 in a 0.18 µm CMOS. To also accommodate the wide-band PRS signals in the IF section of the FE, a highly selective wide-tuning-range 4th-order Gm-C elliptic low-pass filter is used. It features an innovative continuous tuning circuit that adjusts the bias current of the Gm cell¿s input stage to control the cutoff frequency. With this circuit, the power consumption is proportional to the cutoff frequency thus the power efficiency is achieved while keeping the linearity near constant. Thanks to a Gm switching technique, which permit to keep the signal path switchless, the filter shows an extended tuning of the cutoff frequency that covers continuously a range from 7.4 MHz to 27.4 MHz. Moreover the abrupt roll-off of up to 66 dB/octave, can mitigate out-of-band interference. The filter consumes 2.1 mA and 7.5 mA at its lowest and highest cutoff frequencies respectively, and its active area occupies, 0.23 mm2. It achieves a high input-referred third-order intercept point (IIP3) of up to -1.3 dBVRMS

Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors

University of Minnesota Ph.D. dissertation.November 2016. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); x, 137 pages.Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V

Ultra Low-Power Frequency Synthesizers for Duty Cycled IoT radios

Internet of Things (IoT), which is one of the main talking points in the electronics industry today, consists of a number of highly miniaturized sensors and actuators which sense the physical environment around us and communicate that information to a central information hub for further processing. This agglomeration of miniaturized sensors helps the system to be deployed in previously impossible arenas such as healthcare (Body Area Networks - BAN), industrial automation, real-time monitoring environmental parameters and so on; thereby greatly improving the quality of life. Since the IoT devices are usually untethered, their energy sources are limited (typically battery powered or energy scavenging) and hence have to consume very low power. Today's IoT systems employ radios that use communication protocols like Bluetooth Smart; which means that they communicate at data rates of a few hundred kb/s to a few Mb/s while consuming around a few mW of power. Even though the power dissipation of these radios have been decreasing steadily over the years, they seem to have reached a lower limit in the recent times. Hence, there is a need to explore other avenues to further reduce this dissipation so as to further improve the energy autonomy of the IoT node. Duty cycling has emerged as a promising alternative in this sense since it involves radios transmitting very short bursts of data at high rates and being asleep the rest of the time. In addition, high data rates proffer the added advantage of reducing network congestion which has become a major problem in IoT owing to the increase in the number of sensor nodes as well as the volume of data they send. But, as the average power (energy) dissipated decreases due to duty cycling, the energy overhead associated with the start-up phase of the radio becomes comparable with the former. Therefore, in order to take full advantage of duty cycling, the radio should be capable of being turned ON/OFF almost instantaneously. Furthermore, the radio of the future should also be able to support easy frequency hopping to improve the system efficiency from an interference point of view. In other words, in addition to high data rate capability, the next generation radios must also be highly agile and have a low energy overhead. All these factors viz. data rate, agility and overhead are mainly dependent on the radio's frequency synthesizer and therefore emphasis needs to be laid on developing new synthesizer architectures which are also amenable to technology scaling. This thesis deals with the evolution of one such all-digital frequency synthesizer; with each step dealing with one of the aforementioned issues. In order to reduce the energy overhead of the synthesizer, FBAR resonators (which are a class of MEMS resonators) are used as the frequency reference instead of a traditional quartz crystal. The FBAR resonators aid the design of fast-startup oscillators as opposed to the long latency associated with the start-up of the crystal oscillator. In addition, the frequency stability of the FBAR lends itself to open-loop architecture which can support very high data rates. Another advantage of the open-loop architecture is the frequency agility which aids easy channel switching for multi-hop architectures, as demonstrated in this thesis

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform

Nowadays, the rapid development of system-on-chip (SoC) market introduces tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC fabrication process is scaling down to allow higher density of integration but makes the chips more sensitive to the process-voltage-temperature (PVT) variations. A successful IC product not only imposes great pressure on the IC designers, who have to handle wider variations and enforce more design margins, but also challenges the test procedure, leading to more check points and longer test time. To relax the designers’ burden and reduce the cost of testing, it is valuable to make the IC chips able to test and tune itself to some extent. In this dissertation, a fully integrated in-situ design validation and optimization (VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test (BIST) techniques for analog circuits. Based on the data collected from BIST, the error between the measured and the desired performance of the target circuit is evaluated using a cost function. A digital multi-dimensional optimization engine is implemented to adaptively adjust the analog circuit parameters, seeking the minimum value of the cost function and achieving the desired performance. To verify this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip. Apart from the VO system, several improved BIST techniques are also proposed in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration. Moreover, an on-chip RF receiver linearity BIST methodology for continuous and discrete-time hybrid baseband chain is proposed. The proposed receiver chain implements a charge-domain FIR filter to notch the two excitation signals but expose the third order intermodulation (IM3) tones. It simplifies the linearity measurement procedure–using a power detector is enough to analyze the receiver’s linearity. Finally, a low cost fully digital built-in analog tester for linear-time-invariant (LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to measure the delays corresponded to a ramp excitation signal and is able to estimate the pole or zero locations of a low-pass LTI system

저전력, 저면적 유선 송수신기 설계를 위한 회로 기술

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 정덕균.In this thesis, novel circuit techniques for low-power and area-efficient wireline transceiver, including a phase-locked loop (PLL) based on a two-stage ring oscillator, a scalable voltage-mode transmitter, and a forwarded-clock (FC) receiver based on a delay-locked-loop (DLL) based per-pin deskew, are proposed. At first, a two-stage ring PLL that provides a four-phase, high-speed clock for a quarter-rate TX in order to minimize power consumption is presented. Several analyses and verification techniques, ranging from the clocking architectures for a high-speed TX to oscillation failures in a two-stage ring oscillator, are addressed in this thesis. A tri-state-inverter–based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed PLL fabricated in the 65-nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply at 10 GHz. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB. Secondly, a voltage-mode (VM) transmitter which offers a wide operation range of 6 to 32 Gb/s, controllable pre-emphasis equalization and output voltage swing without altering output impedance, and a power supply scalability is presented. A quarter-rate clocking architecture is employed in order to maximize the scalability and energy efficiency across the variety of operating conditions. A P-over-N VM driver is used for CMOS compatibility and wide voltage-swing range required for various I/O standards. Two supply regulators calibrate the output impedance of the VM driver across the wide swing and pre-emphasis range. A single phase-locked loop is used to provide a wide frequency range of 1.5-to-8 GHz. The prototype chip is fabricated in 65-nm CMOS technology and occupies active area of 0.48x0.36 mm2. The proposed transmitter achieves 250-to-600-mV single-ended swing and exhibits the energy efficiency of 2.10-to-2.93 pJ/bit across the data rate of 6-to-32 Gb/s. And last, this thesis describes a power and area-efficient FC receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a DLL-based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-UIpp sinusoidal jitter of 300 MHz.Chapter 1. Introduction 1 1.1. Motivation 1 1.2. Thesis organization 5 Chapter 2. Phase-Locked Loop Based on Two-Stage Ring Oscillator 7 2.1. Overivew 7 2.2. Background and Analysis of a Two-stage Ring Oscillator 11 2.3. Circuit Implementation of The Proposed PLL 25 2.4. Measurement Results 33 Chapter 3. A Scalable Voltage-Mode Transmitter 37 3.1. Overview 37 3.2. Design Considerations on a Scalable Serial Link Transmitter 40 3.3. Circuit Implementation 46 3.4. Measurement Results 56 Chapter 4. Delay-Locked Loop Based Forwarded-Clock Receiver 62 4.1. Overview 62 4.2. Timing and Data Recovery in a Serial Link 65 4.3. DLL-Based Forwarded-Clock Receiver Characteristics 70 4.4. Circuit Implementation 79 4.5. Measurement Results 89 Chapter 5. Conclusion 94 Appendix 96 Appendix A. Design flow to optimize a high-speed ring oscillator 96 Appendix B. Reflection Issues in N-over-N Voltage-Mode Driver 99 Appendix C. Analysis on output swing and power consumption of the P-over-N voltage-mode driver 107 Appendix D. Loop Dynamics of DLL 112 Bibliography 121 Abstract 128Docto