Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology

Voltage reference circuit is important in electronic world nowadays. A CMOS based bandgap reference (BGR) circuit is preferred due to its size is smaller and consume less power. However, the drawback is the reference voltage variation of CMOS based BGR circuit is big in wide range of temperature, thus the temperature coefficient of it is high. Hence, an improved version of piecewise curvature-corrected Bandgap voltage reference circuit which has low voltage variation in wide range of temperature is introduced in this project to overcome the problem mentioned above. The BGR circuit is designed using CMOS compatible process in 0.18μm CMOS process technology and simulated by using Cadence tool. The proposed piecewise curvature-corrected BGR operate properly with output voltage of 558.6 mV to 558.3 mV by varying the voltage supply 1.4 V to 3.3 V at 27°C and the line regulation is 0.016% . Besides that, the best temperature coefficient obtained is 9.2 ppm/°C in the temperature range of -25°C to 150°C at 1.8 V. The PSSR of the proposed circuit is -69.91 dB at frequency less 10 kHz. The layout design of the proposed circuit is done by using Silterra 0.18 μm standard CMOS process and total die area is 0.0175 mm2 and temperature coefficient obtained in post layout simulation is 11.66ppm/°C. In short, it is found that the proposed design of BGR circuit is able to achieve high temperature range and relatively low voltage variation

Low Power, High PSR CMOS Voltage References

With integration of various functional modules such as radio frequency (RF) circuits, power management, and high frequency digital and analog circuits into one system on chip (SoC) in recent applications, power supply noise can cause significant system performance deterioration. This makes supply noise rejection of the embedded voltage reference crucial in modern SoC applications. Also the use of resistors in bandgap voltage references makes them less suitable for modern low power and portable applications. This thesis introduces two resistorless sub-1 V, all MOSFET references. The goal is to achieve a high power supply rejection (PSR) over a wide bandwidth not achieved in previous works. This high PSR over wide bandwidth is achieved by using a combination of a feedback technique and an innovative compact MOSFET low pass filter. The two references were fabricated in a standard 0.18 µm CMOS process. The first reference uses a composite transistor in subthreshold to produce a proportional-to-absolute temperature (PTAT) voltage which is converted to a current used to thermally compensate the threshold voltage of a MOSFET in saturation. The second references uses dynamic-threshold voltage MOSFET (DTMOS) to produce a PTAT voltage which is converted to a current used to thermally compensate the threshold voltage of a MOSFET in saturation. The measurement shows that both references consumes a sub-1 µW power across their entire operating temperatures. The first reference achieves a PSR better than 50 dB for frequencies of up to 70 MHz and a 20 ppm/°C temperature coefficient (TC) for temperatures from -35 °C — 80 °C. It has a compact area of 0.0180 mm2 and operates on a supply of 1.2 V — 2.3 V. The second reference achieves a PSR better than 50 dB for frequencies of up to 60 MHz. This reference achieves a TC of 9.33 ppm/°C after trimming for temperatures from -30 °C — 110 °C and a line regulation of 0.076 %/V for a step from 0.8 V to 2 V supply voltage with 360 nW power consumption at room temperature. It has a compact area of 0.0143 mm^2

A low noise, sub-1ppm/oC piecewise second-order curvature compensated bandgap reference for high resolution ADC

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 김수환.본 논문에서는 고해상도 analog to digital converter를 위한 저 잡음, 고 정밀 bandgap voltage reference를 제안한다. reference 회로의 성능 중 가장 중요한 것들은 바로 낮은 온도 계수(temperature coefficient)와 저주파 대역의 전기적 잡음이다. 제안된 Bandgap reference 회로는 위 두가지 요소를 개선 하였다. 먼저 낮은 온도 계수를 성취하기 위해서는 BJT Emitter-Base전압의 비선형적 온도의존성을 보상해주어야 하고, bandgap core을 이루는 Error amplifier의 DC offset을 제거해야 하며, 마지막으로 process variation에의한 추가적인 온도 의존성을 상쇄시켜야 한다. 제안된 bandgap reference는 여러가지 회로 기술들을 활용해 위 요소들을 보상하였다. BJT Emitter-Base전압의 비선형적 온도 의존성을 온도에 대해 2차 의존성을 갖는 compensation 전류를 생성하고 bandgap core에 흘려주어 제거하였다. Compensation 전류는 크게 current subtraction 동작과 current squaring 동작을 통해 생성되는데, 위 동작은 모두 process variation에 둔감하다. 두 번 째로 process variation에 의한 온도 특성의 변화를 보상해 주기 위해 trimming resistor를 사용하였다. 마지막으로 error amplifier에 chopping을 적용하여 Error amplifier DC offset을 약화시켰다. Bandgap reference의 저 주파수 전기적 잡음의 근원은 대부분 Error amplifier이므로 chopping 동작을 통해 저주파대역의 전기적 잡음 또한 제거된다. Chopping 동작을 통해 생겨난 리플 과, 고주파 대역으로 변조된 저주파 대역의 전기적 잡음은 RC filter를 통해 제거하였다. 제안된 bandgap reference는 스탠다드 0.13um CMOS 공정의 3.3V 전원 소자로 설계하였으며 레이아웃 사이즈는 0.0534mm2이다. Post layout simulation 결과 제안된 bandgap reference의 -40°C부터 125°C 사이의 온도 계수는 약 0.64ppm/°C이다. 0.1Hz부터 10Hz사이의 integrated noise는 약 2.7uVrms이다. 제안된 bandgap reference는 상온에서 약 44uA의 전류를 소모한다.In this thesis a low noise and high precision bandgap reference is presented. One of the most important characteristics of reference circuit for analog to digital converter with high resolution is low temperature drift and low noise. The proposed bandgap reference improves these two characteristics. To achieve low temperature coefficient(TC), non-linear temperature dependence of emitter-base voltage of bipolar transistor should be compensated. Also, degradation of TC due to dc offset of the error amplifier and process variation is another concern. The proposed bandgap reference compensates these factors by utilizing various circuit technique. Because non-linear temperature dependence of bipolar transistor has a concave shape with temperature, second order curvature compensation current is generated by using current subtraction circuit and current squaring circuit and injected into bandgap core. The current subtraction and squaring operation is tolerant to process variation. To achieve low temperature coefficient regardless of process variation, PTAT trimming is utilized to compensate added linear temperature dependence. At last, to remove dc offset of the error amplifier, chopping technique is applied to the error amplifier. Ripple and up-modulated low frequency caused by chopping operation is removed through RC-filter. The proposed bandgap reference is designed in 0.13um standard CMOS process. Layout size of the bandgap reference is 0.0534mm2. Post layout simulation shows that TC of the bandgap reference from -40°C to 125 °C is 0.64ppm/°C. In addition, integrated noise from 0.1Hz to 10Hz is about 2.7uVrms. The proposed bandgap reference consumes 44uA at room temperature제 1 장 서론 1 제 1 절 연구의 배경 1 제 2 절 기본적인 bandgap reference의 동작 원리. 4 1. bipolar 트랜지스터의 온도 특성 4 2. 기본적인 bandgap voltage reference의 동작 원리 7 3. 기본적인 bandgap current reference의 동작 원리 9 제 2 장 기본적인 bandgap reference의 성능적 한계 12 제 1 절 비선형적 온도 의존성 12 1. error amplifier dc offset 14 2. emitter-base 전압의 비선형적 온도 의존성 16 3. bipolar 트랜지스터 전류 이득에 의한 비선형적 온도 의존성 17 4. bipolar 트랜지스터의 베이스 저항에 의한 비선형적 온도 의존성 19 제 2 절 Bandgap reference의 전기적 잡음. 20 제 3 장 제안하는 저 잡음 고 정밀 bandgap voltage reference 22 제 1절 제안된 bandgap reference의 전체 구조 22 1. PTAT전류 생성 회로 23 2. reference 전류 생성 회로 24 3. bandgap core 25 제 2절 Curvature compensation technique 25 제 3절 Noise reduction technique 30 제 4절 Resistor trimming 32 제 5절 주요 성분 파라 미터 테이블 33 제 4 장 Layout 및 모의 실험 결과 34 제 1 절 Layout 34 제 2 절 모의 실험 결과 35 제 5 장 결론 40 제 6 장 부록 current squaring 회로의 동작 원리. 41 참고문헌 43 Abstract 43Maste

A low-power native NMOS-based bandgap reference operating from −55°C to 125°C with Li-Ion battery compatibility

Summary The paper describes the implementation of a bandgap reference based on native-MOSFET transistors for low-power sensor node applications. The circuit can operate from −55°C to 125°C and with a supply voltage ranging from 1.5 to 4.2 V. Therefore, it is compatible with the temperature range of automotive and military-aerospace applications, and for direct Li-Ion battery attach. Moreover, the circuit can operate without any dedicated start-up circuit, thanks to its inherent single operating point. A mathematical model of the reference circuit is presented, allowing simple portability across technology nodes, with current consumption and silicon area as design parameters. Implemented in a 55-nm CMOS technology, the voltage reference achieves a measured average (maximum) temperature coefficient of 28 ppm/°C (43 ppm/°C) and a measured sample-to-sample variation within 57 mV, with a current consumption of 420 nA at 27°C

Bandgap Reference Design at the 14-Nanometer FinFET Node

As supply voltages continue to decrease, it becomes harder to ensure that the voltage drop across a diode-connected BJT is sufficient to conduct current without sacrificing die area. One such solution to this potential problem is the diode-connected MOSFET operating in weak inversion. In addition to conducting appreciable current at voltages significantly lower than the power supply, the diode-connected MOSFET reduces the total area for the bandgap implementation. Reference voltage variations across Monte Carlo perturbations are more pronounced as the variation of process parameters are exponentially affected in subthreshold conduction. In order for this proposed solution to be feasible, a design methodology was introduced to mitigate the effects of process variation. A 14 nm bandgap reference was created and simulated across Monte Carlo perturbations for 100 runs at nominal supply voltage and 10% variation of the power supply in either direction. The best case reference voltage was found and used to verify the proposed resistive network solution. The average temperature coefficient was measured to be 66.46 ppm/◦C and the voltage adjustment range was found to be 204.1 mV. The two FinFET subthreshold diodes consume approximately 2.8% of the area of the BJT diode equivalent. Utilizing an appropriate process control technique, subthreshold bandgap references have the potential to overtake traditional BJT-based bandgap architectures in low-power, limited-area applications

Amplificador de tensão com curva de ganho aproximada por partes

Automatic Gain Control (AGC) is a system that provides a gain variation of an amplifier from a control signal. This dissertation presents the project of a voltage amplifier with non-linear gain curve using linear piecewise approximation controlled by a AGC system. The gain curve was reconstructed from experimental values. The technique used enabled the implementation of an analog curve by adding the sum of line segments by varying the start points and the angular coefficients. The results obtained from simulations and practical tests showed that the amplifier has the voltage gain as a function of the control voltage following the piecewise approximate. The gain varied between 4 and 0 in a non-linear way controlled by a control voltage variable between 0 and 4 V. The maximum input excursion of the amplifier is 2 VPP and the maximum output excursion of 7.5 VPPControle Automático de Ganho (CAG) é um sistema que proporciona uma variação de ganho de um amplificador a partir de um sinal de controle. Esta dissertação apresenta o projeto de um amplificador de tensão com curva de ganho não linear aproximada por partes controlado por um sistema de CAG. A curva de ganho foi reconstruída a partir de valores obtidos experimentalmente. A técnica utilizada capacitou a implementação de uma curva analógica fazendo-se o somatório de segmentos de reta variando-se os pontos de início e os coeficientes angulares. Os resultados obtidos a partir de simulações e testes práticos demonstraram que o amplificador possui o ganho de tensão em função da tensão de controle seguindo a curva aproximada por partes. O ganho variou entre 4 e 0 de forma não linear controlado por uma tensão de controle variável entre 0 e 4 V. A excursão máxima de entrada do amplificador é de 2 VPP e a excursão máxima de saída de 7,5 VP

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

Fully Integrated Voltage Reference Circuits

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2014(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2014Gerilim referans devreleri, elektriksel sistemlerde diğer alt blokların çalışmaları için kararlı bir çalışma noktası üretmeleri sebebiyle veri dönüştürücüler (ADC - DAC), frekans sentezleyiciler, DC-DC ve AC-DC dönüştürücüler ve lineer regülatörler gibi pek çok elektriksel sistemin en temel yapı bloklarındandır. İdeal olarak, üretilen bu referans noktası, sıcaklık, üretim süreçleri, besleme gerilim degişimleri ve yükleme etkileri gibi çalışma koşullarından etkilenmemelidir. Bir referans devresinin doğruluğu bahsedilen çalışma koşullarının etkisiyle mutlak değerinden ne kadar saptığı olarak tanımlanır. Modern haberleşme sistemleri ve tüketici ürünlerindeki gelişmeler ile birlikte yüksek entegrasyon ve doğruluklu sistemlere olan talep artmıştır. Tümdevre sistemlerinde, alt blokların çalışma noktalarını belirlemesi nedeniyle özellikle referans devrelerinin performansları bütün sistemin performansının belirlenmesinde önemli rol oynamaktadır. Dolayısıyla yüksek performanslı sistemlere olan talep, bu performansların elde edilmesi için kullanılan düşük geometrili üretim teknolojilerine uygun, yani giderek azalan besleme gerilimleri ile çalışabilecek yüksek doğruluklu referans devrelerine olan talebi de arttırmıştır. Bu nedenle bu çalışmada gerilim referans devre topolojilerine odaklanılmıştır. Bu doğrultuda, öncelikle yüksek doğruluklu, düşük gürültülü gerilim refereans devre topolojileri üzerinde çalışılarak 0.35 um CMOS teknoljisinde farklı tasarımlar yapılmıştır. Bu aşamada temel hedef, yüksek dogrulukluk olarak belirenmiş ve yapılan tasarımlarda, üretim sonrası ayarlamalardan sonra sıcaklık katsayısı 3 ppm/C olabilecek devreler tasarlanmıştır. Ancak, 0.35 um CMOS üretim teknolojisi kullanılması ve kullanılan topolojiler dolayısıyla, devrelerin çalışabileceği minimum besleme gerilim seviyesi 1.8 V ile sınırlı kalmıştır. Devrelerin çektikleri akımlar ise 20-30 uA seviyesindedir. Bu tasarımlar sırasında (triple-well üretim teknlojileri için), önerilen blok gövde izolasyon stratejisi, tasarımı yapılan devrenin gövdesinin tümdevrenin geri kalan kısmından ters kutuplanmış bir jonksiyon diyodu sayesinde izole edilmesine dayanmaktadır ve devrenin gövde gürültüsünden etkilenmesini önemli ölçüde azaltmaktadır. Son olarak, çoğunlukla osilatör devrelerinde uygulanan anahtarlamalı kutuplama tekniği uygulanarak devrelerin düşük frekans gürültü performansının iyileştirilmesi amaçlanmıştır. Çalışmanın geri kalan kısmında, düşük besleme gerilimleriyle çalışabilecek mikron-altı üretim teknolojilerine uygun gerilim referans devre topolojileri üzerine odaklanılmıştır. Bu doğrultuda, iki yeni düşük besleme gerilimli ve düşük güç tüketimli gerilim referans devre topolojisi önerilmiştir. Önerilen topolojiler, 0.18 um CMOS üretim teknolojisinde gerçeklenmiştir. Ölçüm sonuçları, tasarlanan gerilim refarans devrelerinin 0.65 V besleme gerilimi ile çalışabildiğini göstermiştir. Önerilen devre topolojileri ile 0-120 C sıcaklık aralığında, sıcaklık katsayısı 50 ppm/C olan 193 mV seviyesinde referans gerilimleri elde edilmiştir. Devrelerin güç tüketimleri sırasıyla 0.3 uW ve 0.4 uW iken kapladıkları alan 0.2 mm^2 ve 0.08 mm^2 dir. Sonuç olarak, önerilen devre topolojileri ile literatürde yer alan diğer 1V-altı referans devreleri ile karşılatrılabilir seviyede sıcaklık katsayısı olan referans gerilimleri çok daha düşük güç harcamasıyla elde edilmiştir.Voltage references are one of the basic building blocks of many SoCs and mixed-signal ICs such as data converters, voltage regulators and operational amplifiers as they constitute a stable reference voltage for other sub-circuits to generate predictable and repeatable results. Ideally, this reference point should not change with external influences or operating conditions such as temperature, fabrication process variations, power supply variations and transient loading effects. Along with the rapid development of modern communication systems and consumer products, which constitutes the main market for semiconductor industry, the market demand for these System on Chip (SoC) or Mixed Signal ICs to have lower power consumption, higher accuracy and lower cost, and thus, higher integration. Since the performance of the whole system depends strongly to the performance of the reference circuit, this work is focused on fully integrated voltage reference architectures. With this motivation, firstly, different kinds of high precision low noise voltage reference circuits are designed in standard 0.35 um CMOS technology that we have more experience and knowledge of. The essential goal of these studies was high precision and temperature coefficient of the designed voltage reference circuits are on the order of 3 ppm/C with trimming after production. However, since 0.35 um CMOS technology is used in these designs and also due to the chosen topologies their minimum supply voltage can be down to 1.8 V and while current consumption is on the order of 20-30 uA. In the design of the this voltage reference block bulk isolation technique is proposed (for triple-well CMOS processes), in which system blocks are bulk isolated by a reverse biased junction diode from the rest of the die to drastically reduce substrate noise coupling. This is especially important if a very low power voltage reference is designed in a very noisy SoC. Moreover, the switched biasing technique, which is mostly applied to the oscillators, is also implemented to the designed BGR in order to improve the low noise performance of the circuit. The rest of the thesis is focused on new voltage reference topologies that are appropriate for sub-micron technologies operating with low supply voltages. With this motivation two new low voltage and low power voltage reference topologies are proposed. The proposed voltage reference topologies are implemented and fabricated in 0.18 um CMOS technology. Measurement results show that the proposed voltage reference circuits are working properly down to 0.65 V and achieve an output voltage of 193 mV with a temperature coefficient on the order of 50 ppm/C in the temperature range of 0-120C. The total power consumption of the two designed voltage references are 0.3 uW and 0.4 uW at 27 C, while occupying the area of 0.2 mm^2 and 0.08 mm^2, respectively. As a result, the proposed voltage reference topologies generate a reference voltage with comparable level of temperature coefficient and quite low power consumption with respect to the other sub-1V voltage reference circuits reported in the literature.DoktoraPh

A new CMOS voltage reference scheme based on Vth- difference principle

Abstract-a new CMOS voltage reference, which takes advantage of the temperature dependence of NMOS and PMOS threshold voltages, is presented. Due to the circuit architecture the mobility factor is completely cancelled. It does not use resistors and all transistors works in strong inversion. The circuit is simple, opamp-less and can be implemented in a standard CMOS process. When the input power supply changes from 1.8V to 2.1V and the temperature changes from -20 to 80ºC, simulations for the reference circuit using the proposed architecture shows an output voltage of 1.184V and a T FC of 100 ppm/ºC