PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND

The primary objective of this research work is the development of a low power single-lead ECG analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient gain and frequency control mechanism and a low complexity classifier for the detecting asystole, extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the design of a compact single-lead wearable/portable devices with ultra-low-power consumption and in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an efficient automatic gain control mechanism with minimal area overhead and consuming power in the order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR), hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter design, the low pass cut-off frequency is prone to deviate from its nominal value across process and temperature variations. Therefore, post-fabrication calibration is essential, before the signal is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher frequencies into the bandwidth for classification of ECG signals, to switch to low resolution processing, hence saving power and enhances battery lifetime. Another short-coming noticed in the literature published so far is that the classification algorithm is implemented in digital domain, which turns out to be a power hungry approach. Moreover, Although analog domain implementations of QRS complexes detection schemes have been reported, they employ an external micro-controller to determine the threshold voltage. In this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a heart rate estimator is added to the above scheme. It reduces the overall system power consumption by reducing the computational burden on the DSP. The complete proposed scheme consists of (i) an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage, hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis. The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V supply. The functionality of each of the individual blocks are successfully validated using postextraction process corner simulations and through real ECG test signals taken from the PhysioNet database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the measurement results are discussed here. The analog classification scheme is successfully validated using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac

An analogue approach for the processing of biomedical signals

Constant device scaling has signifcantly boosted electronic systems design in the digital domain enabling incorporation of more functionality within small silicon area and at the same time allows high-speed computation. This trend has been exploited for developing high-performance miniaturised systems in a number of application areas like communication, sensor network, main frame computers, biomedical information processing etc. Although successful, the associated cost comes in the form of high leakage power dissipation and systems reliability. With the increase of customer demands for smarter and faster technologies and with the advent of pervasive information processing, these issues may prove to be limiting factors for application of traditional digital design techniques. Furthermore, as the limit of device scaling is nearing, performance enhancement for the conventional digital system design methodology cannot be achieved any further unless innovations in new materials and new transistor design are made. To this end, an alternative design methodology that may enable performance enhancement without depending on device scaling is much sought today.Analogue design technique is one of these alternative techniques that have recently gained considerable interests. Although it is well understood that there are several roadblocks still to be overcome for making analogue-based system design for information processing as the main-stream design technique (e.g., lack of automated design tool, noise performance, efficient passive components implementation on silicon etc.), it may offer a faster way of realising a system with very few components and therefore may have a positive implication on systems performance enhancement. The main aim of this thesis is to explore possible ways of information processing using analogue design techniques in particular in the field of biomedical systems

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

Unsupervised Heart-rate Estimation in Wearables With Liquid States and A Probabilistic Readout

Heart-rate estimation is a fundamental feature of modern wearable devices. In this paper we propose a machine intelligent approach for heart-rate estimation from electrocardiogram (ECG) data collected using wearable devices. The novelty of our approach lies in (1) encoding spatio-temporal properties of ECG signals directly into spike train and using this to excite recurrently connected spiking neurons in a Liquid State Machine computation model; (2) a novel learning algorithm; and (3) an intelligently designed unsupervised readout based on Fuzzy c-Means clustering of spike responses from a subset of neurons (Liquid states), selected using particle swarm optimization. Our approach differs from existing works by learning directly from ECG signals (allowing personalization), without requiring costly data annotations. Additionally, our approach can be easily implemented on state-of-the-art spiking-based neuromorphic systems, offering high accuracy, yet significantly low energy footprint, leading to an extended battery life of wearable devices. We validated our approach with CARLsim, a GPU accelerated spiking neural network simulator modeling Izhikevich spiking neurons with Spike Timing Dependent Plasticity (STDP) and homeostatic scaling. A range of subjects are considered from in-house clinical trials and public ECG databases. Results show high accuracy and low energy footprint in heart-rate estimation across subjects with and without cardiac irregularities, signifying the strong potential of this approach to be integrated in future wearable devices.Comment: 51 pages, 12 figures, 6 tables, 95 references. Under submission at Elsevier Neural Network

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

An Analogue Front-End System with a Low-Power On-Chip Filter and ADC for Portable ECG Detection Devices

Medical diagnostic instruments can be made into portable devices for the purpose of home care, such as the diagnosis of heart disease. These assisting devices are not only used to monitor patients but are also beneficial as handy and convenient medical instruments. Hence, for reasons of both portability and durability, designers should reduce the power consumption of assistant devices as much as possible to extend their battery lifetime. However, achieving the low power requirement of the ECG sensing and the processing board for the ECG with commercial discrete components (A21-0003) is difficult because the low power consumer electronics for ECG acquisition systems are not yet available. With the help of the integrated circuit technology, the power-saving requirement of portable and durable equipment gives circuit designers the impetus to reduce the power consumption of analogue front-end circuits in ECG acquisition systems. In addition, the analogue front-end circuits, which are the interface between physical signals and the digital processor, must be operated at a low-supply voltage to be integrated into the low-voltage system-on-a-chip (SOC) system (Eshraghian, 2006). Therefore, the chapter will present two design examples of low-voltage (1 V) and low-power (<1 W) on-chip circuits including a low-pass filter (LPF) and an analogue-to-digital converter (ADC) to demonstrate the possibility of developing the low-voltage low-power ECG acquisition SO

Biomedical Signal Transceivers

With the growing costs of healthcare, the need for mobile health monitoring devices is critical. A wireless transceiver provides a cost effective way to transmit biomedical signals to the various personal electronic devices, such as computers, cellular devices, and other mobile devices. Different kinds of biomedical signals can be processed and transmitted by these devices, including electroencephalograph (EEG), electrocardiograph (ECG), and electromyography (EMG). By utilizing wireless transmission, the user gains freedom to connect with fewer constraints to their personal devices to view and monitor their health condition. In this chapter, in the first few sections, we will introduce the reader with the basic design of the biomedical transceivers and some of the design issues. In the subsequent sections, we will be presenting design challenges for wireless transceivers, specially using a common wireless protocol Bluetooth. Furthermore, we will share our experience of implementing a biomedical transceiver for ECG signals and processing them. We conclude the discussion with current trends and future work

ULTRA LOW POWER CIRCUITS FOR WEARABLE BIOMEDICAL SENSORS

Ph.DDOCTOR OF PHILOSOPH

CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications

Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non- Linear (ELIN) systems. They can handle large-signals in a low power environment under half the capacitor area required by the more popular ELIN Log-domain filters. Their inherent class-AB nature stems from the odd property of the sinh function at the heart of their companding operation. Despite this early realisation, the Sinh filtering paradigm has not attracted the interest it deserves to date probably due to its mathematical and circuit-level complexity. This Thesis presents an overview of the CMOS weak inversion Sinh filtering paradigm and explains how biomedical systems of low- to audio-frequency range could benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of high order Sinh continuous–time filters and more importantly to confirm their micro-power consumption and 100+ dB of DR through measured results presented for the first time. Novel high order Sinh topologies are designed by means of a systematic mathematical framework introduced. They employ a recently proposed CMOS Sinh integrator comprising only p-type devices in its translinear loops. The performance of the high order topologies is evaluated both solely and in comparison with their Log domain counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a corresponding and also novel Log domain class-AB topology, confirming that Sinh filters constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense of higher complexity and power consumption. The theoretical findings are validated by means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a 0.35μm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of ~60dB and 74μW power consumption from 2V power supply

Investigating the effects of an on-chip pre-classifier on wireless ECG monitoring

In past years, heart disease has been the leading cause of death in most developed countries. Timely detection of a heart condition is necessary in order to prevent life threatening situations. Even when the problem is not a heart condition, the activity of the heart can supply vital information, which makes its monitoring extremely important. A new approach to patient monitoring was taken recently by introducing wireless sensor networks into medical care. The capability of monitoring multiple patients at once makes such a system ideal for pre-hospital and in-hospital emergency care. The main problems associated with wireless sensor networks are power consumption and scaling. The power consumption is a problem due to the need for increased mobility of such a system, while scaling is of concern because a large number of nodes is desired in order to monitor more patients. This thesis addresses the power and bandwidth problems associated with monitoring patients using wireless networks by introducing another level of signal processing at each node. The goal is to design a digital circuit that would detect any abnormality in the ECG signal and enable the data transmission only if such has occurred. Reducing the amount of data being transmitted reduces the necessary bandwidth for each node and with the introduction of the proposed chip, the power consumption of each node is affected as well