A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation

Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm 2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level

Low-voltage Low-power Switched-Capacitor ?S Modulator Design

Ph.DDOCTOR OF PHILOSOPH

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 µW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.This work has been partially funded by Spanish Ministerio de Ciencia e Innovación (MCI), Agencia Estatal de Investigación (AEI) and European Region Development Fund (ERDF/FEDER) under grant RTI2018-097088-B-C3

Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages of the delta-sigma ADC including relaxed anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and most importantly, reduced sensitivity to analog imperfections. In this thesis, several structures and design techniques are developed for the implementation of continuoustime (CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total power consumption, reduce the design complexity, and decrease the chip die area of delta-sigma modulators. First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad (SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of an Nth-order CT delta-sigma modulator, it requires only half the number of active amplifiers and feed-forward branches used in the conventional modulator architecture, thus decreasing the power consumption and area by reducing the number of amplifiers. The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder due to the reduced number of feedforward branches to its summing block. As a sequence, it consumes less power compared to a conventional CT adder. With a 130-nm CMOS technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz signal bandwidth and analog power dissipation lower than 12 mW. Presented as the second scheme to save power consumption and chip die area in ΔΣ modulators is a new stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique shares all the active blocks of the modulator second stage with its first stage during the two non-overlapping clock phases. Measurement results show that the modulator designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz conversion bandwidth dissipating less than 9 mW analog power

LOW POWER ANALOG-TO-DIGITAL CONVERSION CIRCUIT FOR AUDIO APPLICATION

In recent years, demand for a mixed signal LSI used for electronic equipment is increasing. High precision and low power consumption are required for ADCs for audio applications. ΔΣ ADC is a method to realize highly accurate AD conversion. However, power efficiency is poor as compared with general ADC configuration. This paper proposes a two steps ADC using a SAR-ADC and ΔΣ-ADC. The SAR-ADC arranged in the preceding stage can relax the required performance of the analog circuit of ΔΣ ADC. Therefore, low power consumption can be achieved. This proposal is designed with 0.18um CMOS. The performance of proposed system is confirmed by system simulation using MATLAB / Simulink and circuit simulation using Virtuoso / spectre, respectively

A Low Power Sigma-Delta Modulator with Hybrid Architecture

Analogue-to-digital converters (ADC) using oversampling technology and Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using discrete second-order feedforward structure. A 5-bit SAR (Successive-approximation-register) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with Flash ADC type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak SNDR (signal to noise distortion ratio) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve 16-bit ENOB (effective number of bits) when the amplitude of the input signal is varied between 0.15 V to 1.65 V. By comparing with other modulators which were realized by 180nm CMOS process, the proposed architecture outperforms with lower power consumption

Low-voltage low-power continuous-time delta-sigma modulator designs

Ph.DDOCTOR OF PHILOSOPH