Design of a Direct-Modulation Transmitter with Self-Optimizing Feedback and a Highly Linear, Highly Reconfigurable, Continuously-Tunable Active-RC Baseband Filter for Multiple Standards

This work consists of two main parts: i) Design and implementation of a compact current-reusing 2.4GHz direct-modulation transmitter with on-chip automatic tuning; ii) Design and implementation of a novel highly-reconfigurable, continuously tunable, power-adjustable Active-RC filter for multiple standards. The design, analysis, and experimental verification of a proposed self-calibrating, current reused 2.4GHz, direct-modulation transmitter are introduced. A stacked arrangement of the power amplifier/voltage-controlled oscillator is presented along with a novel LC-tank-tuning algorithm with a simple, low-cost, on-chip implementation. To transmit maximum power, the tuning loop ensures the PA's resonant tank is centered around the operating frequency, and the loop requires no ADC, DSP, or external signal generator. This work also details the proposed tuning-loop algorithm and examines the frequency-dependent nonlinear power-detector. The system was implemented in TSMC 0.18[mu]m CMOS, occupies 0.7 mm² (TX) + 0.1 mm² (self tuning), and was measured in a QFN48 package on FR4 PCB. Automatically adjusting the tank-tuning bits within their tuning range results in >4dB increase in output power. With the self-tuning circuit active, the transmitter delivers a measured output power of > 0dBm to a 100-[omega] differential load, and the system consumes 22.9 mA from a 2.2-V supply. A biquad design methodology and a baseband low-pass filter is presented for wireless and wireline applications with reconfigurable frequency response, selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1MHz-20MHz) and adjustable power consumption (3mW-7.5mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel Continuous Impedance Multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and Inverse Chebyshev approximation types. Also, a new stability metric for biquads, Minimum Acceptable Phase Margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3dBm, a THD of -40dB at 447mV[subscript pk, diff] input signal amplitude, and a DR of 71.4dB. The filters tunable range covers frequencies from 1MHz to 20MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than ±2:5%. The design is fabricated in 0.13[mu]m CMOS, occupies 1.53mm², and operates from a 1-V supply

Configurable circuits and their impact on multi-standard RF front-end architectures

This thesis studies configurable circuits and their impact on multi-standard RF front-end architectures. In particular, low-voltage low-power linear LNA and mixer topologies suitable for implementation in multi-standard front-ends are subject of the investigation. With respect to frequency and bandwidth, multi-standard front-ends can be implemented using either tunable or wideband LNA and mixer topologies. Based on the type of the LNA and mixer(s), multi-standard receiver RF front-ends can be divided into three groups. They can be (tunable) narrow-band, wide-band or combined. The advantages and disadvantages of the different multi-standard receiver RF front-ends have been discussed in detail. The partitioning between off-chip selectivity, on-chip selectivity provided by the LNA and mixer, linearity, power consumption and occupied chip area in each multi-standard RF front-end group are thoroughly investigated. A Figure of Merit (FOM) for the multi-standard receiver RF front-end has been introduced. Based on this FOM the most suitable multi-standard RF front-end group in terms of cost-effectiveness can be selected. In order to determine which multi-standard RF front-end group is the most cost-effective for a practical application, a GSM850/E-GSM/DCS/PCS/Bluetooth/WLANa/b/g multi-standard receiver RF front-end is chosen as a demonstrator. These standards are the most frequently used standards in wireless communication, and this combination of standards allows to users almost "anytime-anywhere" voice and data transfer. In order to verify these results, three demonstrators have been defined, designed and implemented, two wideband RF front-end circuits in 90nm CMOS and 65nm CMOS, and one combined multi-standard RF front-end circuit in 65nm CMOS. The proposed multi-standard demonstrators have been compared with the state-of the art narrow-band, wide-band and combined multi-standard RF front-ends. On the proposed multi-standard RF front-ends and the state-of the art multi-standard RF front-ends the proposed FOM have been applied. The comparison shows that the combined multi-standard RF front-end group is the most cost effective multi-standard group for this application

Power-Efficient Design Techniques and Architectures for Scalable Submicron Analog Circuits

As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog) domain into utilizing charge or time as the variable that can be processed by mostly digital/passive circuits. In this thesis, both circuit-level techniques and architectures are proposed that are inherently compatible with transistor scaling in submicron CMOS, meanwhile achieving state-of-the-art performance and optimizing power efficiency. The first part focuses on a highly reconfigurable charge-domain switched-g[subscript m]-C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge sharing technique. It uses only switches, capacitors, linearity-enhanced gm-stages and digital circuitry for a 3-phase non-overlapping clock scheme. Flexible tunability in both center frequency and -3dB bandwidth is achieved with a scaling-compatible implementation. A 4th-order BPF prototype operating at a 1.2GS/s sampling rate is designed with a cascade of two proposed biquads in a 65nm LPE CMOS process. A tunable center frequency of 35−70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The measured in-band IIP3 is +12.5dBm. The filter prototype consumes 7.5mW total power from a 1.2V supply voltage, and occupies a core area of 0.17mm². In the second part, a highly linear continuous-time low-pass filter (LPF) topology with source follower coupling is presented that achieves excellent power efficiency. It synthesizes a 3rd-order low-pass transfer function in a single stage using coupled source followers and three capacitors, and can be configured to 2nd-order by disconnecting a capacitor. A 5th-order Butterworth prototype is designed with a cascade of two proposed filter stages in a 0.18μm CMOS, and occupies a core area of 0.12mm². Operating with a 1.3V supply voltage, the filter consumes only 0.5mA current, and achieves a -3dB bandwidth of 20MHz with 82dB stop-band rejection. A total harmonic distortion (THD) of -39.5dB at the output is measured with a +6.6dBm (i.e. 1.35V[subscript pk-pk]) input signal at 2MHz. The measured in-band IIP3 is +28.8dBm. The dynamic range (at 1% THD) is 76.8dB, with 15.3nV/√Hz averaged in-band input-referred noise. A pseudo-differential-VCO based 2nd-order continuous-time ΔΣ ADC with a residue self-coupling technique is proposed and implemented with mostly digital circuits in the third part. Two VCOs are arranged in a pseudo-differential manner. The digital output is obtained by comparing the sampled output phase of one VCO with that of the other. Passive subtraction is realized in current domain to obtain the residue at the VCO input. The residue self-coupling is implemented using a linear 1st-order transconductance low-pass filter (TCLPF). Moreover, a highly linear VCO topology is presented. The transistor-level simulations in a 65nm CMOS process show a 78dB SNDR over a 10MHz signal bandwidth with a power consumption of 2.9mW, which is 16dB improvement in contrast to the case with the TCLPF block powered off

Integrinių analoginių filtrų belaidžio ryšio sistemoms kūrimas

Disertacijoje nagrinėjami konfigūruojami analoginiai filtrai su savaiminio derinimo grandynais, jų projektavimo ir įgyvendinimo būdai, kurie pritaikomi integrinių grandynų gamybos technologijoms. Iškeliama ir įrodoma hipotezė, teigianti, kad savaiminio derinimo grandynų taikymas įgalina gauti integrinių analoginių aktyviųjų rezistorių kondensatorių (RC) filtrų parametrus reikalau¬jamu tikslumu. Darbo tikslas – sukurti savaiminio derinimo grandynus, skirtus konfigūruojamų integrinių analoginių aktyviųjų RC filtrų parametrų gavybai reikalaujamu tikslumu. Darbe išspręsti uždaviniai: ištirtos integrinių analoginių aktyviųjų RC filtrų struktūros ir sukurti jų derinimo grandynų modeliai, pasiūlytas integrinių analoginių aktyviųjų RC filtrų derinimo matricų projektavimo būdas, sukurtas ir ištirtas konfigūruojamas integrinis analoginis aktyvusis RC filtras su diskrečiu ir tolydžiu savaiminio derinimo grandynais. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatū¬ros ir autoriaus publikacijų disertacijos tema sąrašai ir penki priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašomas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma tyrimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, ginamieji teiginiai, disertacijos struktūra. Pirmame skyriuje apžvelgiamos integrinių analoginių filtrų struktūros, pagrindiniai parametrai bei įvardijamos parametrų verčių svyravimo priežastys, analizuojamos savaiminio derinimosi grandynų struktūros ir jų veikimo principai. Skyriaus pabaigoje, remiantis atlikta analize ir sudarytomis išvadomis suformuluojami disertacijos uždaviniai. Antrajame skyriuje sudaroma konfigūruojamo integrinio analoginio filtro struktūra, skirta programine įranga valdomam radijui, sudaromi diskretaus ir tolydaus derinimo matricų modeliai, juos sudarančių elementų verčių parinkimo algoritmai, atliekami modelių ir algoritmų kompiuteriniai skaičiavimai. Trečiajame skyriuje, pasinaudojus sukurtais modeliais ir algoritmais, suprojektuojamas filtras su diskrečiu ir tolydžių savaiminio derinimo grandynais, naudojant eksperimentinius ir kompiuterinius skaičiavimo metodus atliekamas suprojektuotų diskrečiai ir tolydžiai valdomų integrinių analoginių RC filtrų parametrų bei jų savaiminio derinimo grandynų tyrimas. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: du – mokslo žurnaluose, įtrauktuose į Thomson Reuters Web of Science duomenų bazę, vienas – tarptautinių konferencijų medžiagoje, įtrauktoje į Thomson Reuters Proceedings duomenų bazę, keturi – mokslo žurnaluose, referuojamose kitose tarptautinėse duomenų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo pristatyti septyniose mokslinėse konferencijose Lietuvoje ir užsienyje

Low-Power Wireless Medical Systems and Circuits for Invasive and Non-Invasive Applications

Approximately 75% of the health care yearly budget of public health systems around the world is spent on the treatment of patients with chronic diseases. This, along with advances on the medical and technological fields has given rise to the use of preventive medicine, resulting on a high demand of wireless medical systems (WMS) for patient monitoring and drug safety research. In this dissertation, the main design challenges and solutions for designing a WMS are addressed from system-level, using off-the-shell components, to circuit implementation. Two low-power oriented WMS aiming to monitor blood pressure of small laboratory animals (implantable) and cardiac-activity (12-lead electrocardiogram) of patients with chronic diseases (wearable) are presented. A power consumption vs. lifetime analysis to estimate the monitoring unit lifetime for each application is included. For the invasive/non-invasive WMS, in-vitro test benches are used to verify their functionality showing successful communication up to 2.1 m/35 m with the monitoring unit consuming 0.572 mA/33 mA from a 3 V/4.5 V power supply, allowing a two-year/ 88-hour lifetime in periodic/continuous operation. This results in an improvement of more than 50% compared with the lifetime commercial products. Additionally, this dissertation proposes transistor-level implementations of an ultra-low-noise/low-power biopotential amplifier and the baseband section of a wireless receiver, consisting of a channel selection filter (CSF) and a variable gain amplifier (VGA). The proposed biopotential amplifier is intended for electrocardiogram (ECG)/ electroencephalogram (EEG)/ electromyogram (EMG) monitoring applications and its architecture was designed focused on improving its noise/power efficiency. It was implemented using the ON-SEMI 0.5 µm standard process with an effective area of 360 µm2. Experimental results show a pass-band gain of 40.2 dB (240 mHz - 170 Hz), input referred noise of 0.47 Vrms, minimum CMRR of 84.3 dBm, NEF of 1.88 and a power dissipation of 3.5 µW. The CSF was implemented using an active-RC 4th order inverse-chebyshev topology. The VGA provides 30 gain steps and includes a DC-cancellation loop to avoid saturation on the sub-sequent analog-to-digital converter block. Measurement results show a power consumption of 18.75 mW, IIP3 of 27.1 dBm, channel rejection better than 50 dB, gain variation of 0-60dB, cut-off frequency tuning of 1.1-2.29 MHz and noise figure of 33.25 dB. The circuit was implemented in the standard IBM 0.18 µm CMOS process with a total area of 1.45 x 1.4 mm^(2). The presented WMS can integrate the proposed biopotential amplifier and baseband section with small modifications depending on the target signal while using the low-power-oriented algorithm to obtain further power optimization