4,480 research outputs found

    System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

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    This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

    Analog sinewave signal generators for mixed-signal built-in test applications

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    This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators—a continuous-time generator and a discrete-time one—have been integrated in a standard 0.35 μm CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.Gobierno de España TEC2007-68072/MIC, TSI-020400-2008-71/MEDEA+2A105, CATRENE CT302Junta de Andalucía P09-TIC-538

    Advanced modulation technology development for earth station demodulator applications

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    The purpose of this contract was to develop a high rate (200 Mbps), bandwidth efficient, modulation format using low cost hardware, in 1990's technology. The modulation format chosen is 16-ary continuous phase frequency shift keying (CPFSK). The implementation of the modulation format uses a unique combination of a limiter/discriminator followed by an accumulator to determine transmitted phase. An important feature of the modulation scheme is the way coding is applied to efficiently gain back the performance lost by the close spacing of the phase points

    A BIST solution for frequency domain characterization of analog circuits

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    This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1storder Ă“Ă„ modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35ìm-3.3V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of [email protected] (1MHz clock) has been demonstrated.Gobierno de España TEC2007-68072/MIC, TSI 020400- 2008-71Catrene European Project 2A105SR

    Mesoscale Ceramic Cylindrical Ion Trap Mass Analyzers For In Situ Sample Analysis

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    As wireless network devices and IOT connectivity develop, the application and demand for small, low power, in situ sensors and instruments will expand. There are continuous efforts in the miniaturization of sensors and scientific instrument systems for conventional to field deployable and rugged hand held units for personal use to extreme harsh environment applications. This work investigates mesoscale cylindrical ion trap (CIT) mass analyzer design and the benefits of CITs realized via additive manufactured metalized ceramic material systems for improved ion signal, low power performance, and extended dynamic range. Rugged monolithic miniature mass spectrometer ceramic CIT chips have been produced that have increased signal output with reduced power consumption. We have demonstrated via simulation and experiment ~80% and greater CIT ion detection efficiency, signal improvement of the percentage of analyzed ions detected, from 50% detection for conventional CIT designs. Utilizing a unique notched ring electrode design that increases the ion signal output to the detector, the electron ionization quantity and power required for mass spectrum generation and tuning was reduced by ~1 watt or 33%, as well as the required gain of the ion detector. Increased CIT ion detection efficiency effectively increases the total amount of the sample analyzed versus what is lost, thus increasing the instrument sensitivity and data collected, reducing duty cycle and power. Identical CITs of a ring electrode radius, ro = 1 mm, were fabricated from low temperature co-fired ceramic (LTCC) and the stainless steel (SS) for performance comparison and were tested in mass instability scanning and resonance ejection modes to produce Perfluorotribuytlamine (PFTBA) mass spectra. The ceramic material system offers design anFd material benefits which reduce the CIT power consumption by 29x from ~10.20 mW power consumption of the stainless steel CIT design to 0.36 mW for the ceramic CIT, as well as enabling batch fabrication, reduced cost and manufacturing defects. While the stated design and material system benefits may facilitate CIT and MS system miniaturization, and the production of the ceramic CIT chip, the proof of concept of CIT ion ejection efficiency via the notched ring electrode may enhance ion trap designs at any scale

    Electrophoretic deposition of ferrite

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    The ability to integrate a material with a high permeability on chip, allows for magnetically coupled circuits and structures to be designed and incorporated along side CMOS circuitry. Devices ranging from A.C. transformers to magnetically driven MEMS structures can be designed and fabricated. Desirable characteristics of magnetic cores for integrated inductors and transformers are first high saturation flux in order to obtain high saturation current; high permeability to obtain high inductance; high resistivity to reduce eddy current loss at high frequencies and compatible deposition and patterning processes. High frequency magnetic materials are oxide based ceramics and are therefore difficult to evaporate, sputter, plate and selectively etched. ElectroPhoretic Deposition (EPD) is a method where insulating particles are imparted charge in a suspension and are made to deposit on an electrode by applying electric field. EPD has been extensively employed in depositing oxide based phosphors for display applications. In this study, ferrite particles have been prepared by grinding sintered toroids and deposited by EPD. The electrophoretic solution bath is composed of isopropyl alcohol with traces of Mg(N03)2 and La(N03)3 salts. Glycerol is added to the solution bath as a surfactant to promote increased substrate adhesion. The dissociation of magnesium nitrate in the solution bath charges the ferrite particles. An electric field of ~ 50-160 V/cm is applied with negative terminal connected to the wafer to be plated and aluminum electrode is used as the anode. The deposition process is found to be self limiting with the initial high elerophoretic current declining to 10% of its value in 10 minutes. The deposition rate and zeta potential measurements indicate a high particle velocity on the order 5.7x10-3 cm/s with an electric field of 160V/cm generated across the 2 cm electrode spacing. Pattern filling and conformal coverage in copper damascene planar microinductors has been investigated. A method to extracted permeability from S11 impedance analysis has been employed. It has been found that grinding process deteriorates magnetic response. With recent advances in magnetic particle technology for high frequency materials, these results enable unique hard and soft powder ferrite material to be selectively deposited in wide variety of CMOS and MEM’s based applications

    Comb-based WDM transmission at 10 Tbit/s using a DC-driven quantum-dash mode-locked laser diode

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    Chip-scale frequency comb generators have the potential to become key building blocks of compact wavelength-division multiplexing (WDM) transceivers in future metropolitan or campus-area networks. Among the various comb generator concepts, quantum-dash (QD) mode-locked laser diodes (MLLD) stand out as a particularly promising option, combining small footprint with simple operation by a DC current and offering flat broadband comb spectra. However, the data transmission performance achieved with QD-MLLD was so far limited by strong phase noise of the individual comb tones, restricting experiments to rather simple modulation formats such as quadrature phase shift keying (QPSK) or requiring hard-ware-based compensation schemes. Here we demonstrate that these limitations can be over-come by digital symbol-wise phase tracking algorithms, avoiding any hardware-based phase-noise compensation. We demonstrate 16QAM dual-polarization WDM transmission on 38 channels at an aggregate net data rate of 10.68 Tbit/s over 75 km of standard single-mode fiber. To the best of our knowledge, this corresponds to the highest data rate achieved through a DC-driven chip-scale comb generator without any hardware-based phase-noise reduction schemes

    Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

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    This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin
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