105 research outputs found
A Low-Power Sigma-Delta Modulator for Healthcare and Medical Diagnostic Applications
This paper presents a switched-capacitor Sigma-Delta modulator designed in 90-nm CMOS technology, operating at 1.2-V supply voltage. The modulator targets healthcare and medical diagnostic applications where the readout of small-bandwidth signals is required. The design of the proposed A/D converter was optimized to achieve the minimum power consumption and area. A remarkable performance improvement is obtained through the integration of a low-noise amplifier with modified Miller compensation and rail-to-rail output stage. The manuscript also presents a set of design equations, from the small-signal analysis of the amplifier, for an easy design of the modulator in different technology nodes. The Sigma-Delta converter achieves a measured 96-dB dynamic range, over a 250-Hz signal bandwidth, with an oversampling ratio of 500. The power consumption is 30 μW, with a silicon area of 0.39 mm²
Low-pass CMOS Sigma-Delta Converter
A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante.
O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução.
Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance .
Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution.
This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption
Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators
RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs
Design of a Comparator and an Amplifier in CMOS using standard logic gates
Using standard logic gates in CMOS, or standard-cells, has the advantage of full synthe-
sizability, as well as the voltage scalability between technologies. In this work a general pur-
pose standard-cell-based voltage comparator and amplifier are presented.
The objective is to design a general purpose standard-cell-based comparator and ampli-
fier in 130 nm CMOS by optimizing the already existing topologies with the aim of improving
some of the specifications of the studied topologies.
Various simulation testbenches were made to test the studied topologies of comparators
and amplifiers, in which the results were compared. The top performing standard-cell com-
parator and amplifier were then modified. After successfully designing the comparator, it was
used in the design of an opamp-less Sigma-Delta modulator (ΣΔM).
The proposed comparator is an OR-AND-Inverter-based comparator with dual inputs
and outputs, achieving a delay of 109 ps, static input offset of 591 μV, and random offset of
10.42 μV, while dissipating 890 μW, when clocked at 1.5 GHz.
The proposed amplifier is a single-path three-stage inverter-based operational transcon-
ductance amplifier (OTA) with active common-mode feedback loop, achieving a DC gain of
63 dB, 1444 MHz of unity-gain bandwidth, 51º of phase margin while dissipating 1098 μW,
considering a load of 1 pF.
The proposed comparator was employed in the ΣΔM with a standard-cell based edge-
triggered flip-flop. The ΣΔM, with a sampling frequency of 2 MHz and a signal bandwidth of
2.5 kHz, achieved a peak SNDR of 69 dB while dissipating only 136.7 μW.Utilizando portas lógicas básicas em CMOS oferece a vantagem de um circuito comple-
tamente sintetizável, tal como o escalamento de tensão entre tecnologias. Neste trabalho são
apresentados um comparador de tensão e um amplificador utilizando portas lógicas.
O objetivo deste trabalho é desenhar um comparador e um amplificador utilizando por-
tas lógicas através do estudo e otimização de topologias já existentes com a finalidade de me-
lhoramento de algumas das especificações das mesmas.
Foram realizados vários bancos de teste para testar as topologias estudadas de compa-
radores e amplificadores, em que os resultados foram comparados. As topologias de compa-
radores e amplificadores de portas lógicas com melhor performance foram então modificadas.
Após o comparador ter sido projetado com sucesso, foi utilizado na projeção de um modula-
dor
Sigma-Delta (ΣΔM)
opamp-less.
O comparador proposto é um
OR-AND-Inversor com duas entradas e saídas, que apre-
senta um atraso de 109 ps,
offset estático na entrada de 591 μV,
offset aleatório de 10.42 μV,
enquanto dissipando 890 μW, utilizando uma frequência de relógio de 1.5 GHz
O amplificador proposto é um amplificador operacional de transcondutância
single-
path three-stage inverter-based com um
loop ativo de realimentação do modo-comum, que
apresenta um ganho DC de 63 dB, 1444 MHz de ganho-unitário de largura de banda, 51º de
margem de fase e dissipando 1098 μW, considerando uma carga de 1 pF.
O comparador proposto foi aplicado no ΣΔM com um
flip-flop edge-triggered baseado
em portas lógicas. O ΣΔM, com uma frequência de amostragem de 2 MHz e uma largura de
banda de 2.5 kHz, apresentou um SNDR máximo de 69 dB enquanto dissipando apenas 136.7
μW
Low-voltage low-power continuous-time delta-sigma modulator designs
Ph.DDOCTOR OF PHILOSOPH
A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications
This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution and power consumption in various smart sensor applications. It mainly consists of an incremental delta???sigma modulator and the proposed SAR-EC sub-ADC for alternate operation of the coarse SAR conversion and EC. They can be reconfigured to operate separately depending on the application requirements. The SAR-based zooming structure allows the IADC to have better linearity and resolution, and additional activation of the EC function gives the further resolution. During this reconfigurable conversion process, pipelined reusing operation of sub-blocks reduces the silicon area and the number of cycles for target resolutions. A prototype ADC is fabricated in a 180-nm CMOS process, and its triple-mode operation of high-resolution, medium-resolution, and low-power is experimentally verified to achieve 116.1-, 109.4-, and 73.3-dB dynamic ranges, consuming 1.60, 1.26, and 0.39 mW, respectively
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Digital Solutions for Analog Shortcomings in Delta-Sigma Analog-to-Digital Converters
Portable, high power efficiency communication devices is a growing market in the semiconductor industry. Analog-to-digital converters (ADC) are key interface that are used to digitize the sensed information. Recently, digital techniques have been proposed to improve analog building block power efficiency in sub-micron technologies. This research focuses on mixed signal approaches to improve the power efficiency of the noise shaping ADCs and mitigate analog inaccuracies such as non-linearity and mismatch. First, a novel continuous-time filtering delta-sigma ADC is proposed to save power and area. Digital techniques have been proposed to make the architecture more robust to out-of-band unwanted signals. A prototype was fabricated in a 65 nm CMOS technology achieving an SNDR of 72.4 dB operating at 250 MHz sampling frequency over 7 MHz bandwidth, with a power consumption of 16.3 mW. Next, A novel digital circuitry is proposed to improve the tolerance of a discrete-time delta sigma ADC to mismatch and enhance the resolution of an ADC in the presence of mismatch. A custom IC was fabricated in a 65 nm CMOS technology consuming 40.4 μA from a 1 V supply. It achieves 76.18 dB SNDR operating at 1.2 MHz sampling frequency and 25 kHz signal bandwidth
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