Low-Power Human-Machine Interfaces: Analysis And Design

Human-Machine Interaction (HMI) systems, once used for clinical applications, have recently reached a broader set of scenarios, such as industrial, gaming, learning, and health tracking thanks to advancements in Digital Signal Processing (DSP) and Machine Learning (ML) techniques. A growing trend is to integrate computational capabilities into wearable devices to reduce power consumption associated with wireless data transfer while providing a natural and unobtrusive way of interaction. However, current platforms can barely cope with the computational complexity introduced by the required feature extraction and classification algorithms without compromising the battery life and the overall intrusiveness of the system. Thus, highly-wearable and real-time HMIs are yet to be introduced. Designing and implementing highly energy-efficient biosignal devices demands a fine-tuning to meet the constraints typically required in everyday scenarios. This thesis work tackles these challenges in specific case studies, devising solutions based on bioelectrical signals, namely EEG and EMG, for advanced hand gesture recognition. The implementation of these systems followed a complete analysis to reduce the overall intrusiveness of the system through sensor design and miniaturization of the hardware implementation. Several solutions have been studied to cope with the computational complexity of the DSP algorithms, including commercial single-core and open-source Parallel Ultra Low Power architectures, that have been selected accordingly also to reduce the overall system power consumption. By further adding energy harvesting techniques combined with the firmware and hardware optimization, the systems achieved self-sustainable operation or a significant boost in battery life. The HMI platforms presented are entirely programmable and provide computational power to satisfy the requirements of the studies applications while employing only a fraction of the CPU resources, giving the perspective of further application more advanced paradigms for the next generation of real-time embedded biosignal processing

Ultra low power wearable sleep diagnostic systems

Sleep disorders are studied using sleep study systems called Polysomnography that records several biophysical parameters during sleep. However, these are bulky and are typically located in a medical facility where patient monitoring is costly and quite inefficient. Home-based portable systems solve these problems to an extent but they record only a minimal number of channels due to limited battery life. To surmount this, wearable sleep system are desired which need to be unobtrusive and have long battery life. In this thesis, a novel sleep system architecture is presented that enables the design of an ultra low power sleep diagnostic system. This architecture is capable of extending the recording time to 120 hours in a wearable system which is an order of magnitude improvement over commercial wearable systems that record for about 12 hours. This architecture has in effect reduced the average power consumption of 5-6 mW per channel to less than 500 uW per channel. This has been achieved by eliminating sampled data architecture, reducing the wireless transmission rate and by moving the sleep scoring to the sensors. Further, ultra low power instrumentation amplifiers have been designed to operate in weak inversion region to support this architecture. A 40 dB chopper-stabilised low power instrumentation amplifiers to process EEG were designed and tested to operate from 1.0 V consuming just 3.1 uW for peak mode operation with DC servo loop. A 50 dB non-EEG amplifier continuous-time bandpass amplifier with a consumption of 400 nW was also fabricated and tested. Both the amplifiers achieved a high CMRR and impedance that are critical for wearable systems. Combining these amplifiers with the novel architecture enables the design of an ultra low power sleep recording system. This reduces the size of the battery required and hence enables a truly wearable system.Open Acces

Design and Implementation of Complexity Reduced Digital Signal Processors for Low Power Biomedical Applications

Wearable health monitoring systems can provide remote care with supervised, inde-pendent living which are capable of signal sensing, acquisition, local processing and transmission. A generic biopotential signal (such as Electrocardiogram (ECG), and Electroencephalogram (EEG)) processing platform consists of four main functional components. The signals acquired by the electrodes are amplified and preconditioned by the (1) Analog-Front-End (AFE) which are then digitized via the (2) Analog-to-Digital Converter (ADC) for further processing. The local digital signal processing is usually handled by a custom designed (3) Digital Signal Processor (DSP) which is responsible for either anyone or combination of signal processing algorithms such as noise detection, noise/artefact removal, feature extraction, classification and compres-sion. The digitally processed data is then transmitted via the (4) transmitter which is renown as the most power hungry block in the complete platform. All the afore-mentioned components of the wearable systems are required to be designed and fitted into an integrated system where the area and the power requirements are stringent. Therefore, hardware complexity and power dissipation of each functional component are crucial aspects while designing and implementing a wearable monitoring platform. The work undertaken focuses on reducing the hardware complexity of a biosignal DSP and presents low hardware complexity solutions that can be employed in the aforemen-tioned wearable platforms. A typical state-of-the-art system utilizes Sigma Delta (Σ∆) ADCs incorporating a Σ∆ modulator and a decimation filter whereas the state-of-the-art decimation filters employ linear phase Finite-Impulse-Response (FIR) filters with high orders that in-crease the hardware complexity [1–5]. In this thesis, the novel use of minimum phase Infinite-Impulse-Response (IIR) decimators is proposed where the hardware complexity is massively reduced compared to the conventional FIR decimators. In addition, the non-linear phase effects of these filters are also investigated since phase non-linearity may distort the time domain representation of the signal being filtered which is un-desirable effect for biopotential signals especially when the fiducial characteristics carry diagnostic importance. In the case of ECG monitoring systems the effect of the IIR filter phase non-linearity is minimal which does not affect the diagnostic accuracy of the signals. The work undertaken also proposes two methods for reducing the hardware complexity of the popular biosignal processing tool, Discrete Wavelet Transform (DWT). General purpose multipliers are known to be hardware and power hungry in terms of the number of addition operations or their underlying building blocks like full adders or half adders required. Higher number of adders leads to an increase in the power consumption which is directly proportional to the clock frequency, supply voltage, switching activity and the resources utilized. A typical Field-Programmable-Gate-Array’s (FPGA) resources are Look-up Tables (LUTs) whereas a custom Digital Signal Processor’s (DSP) are gate-level cells of standard cell libraries that are used to build adders [6]. One of the proposed methods is the replacement of the hardware and power hungry general pur-pose multipliers and the coefficient memories with reconfigurable multiplier blocks that are composed of simple shift-add networks and multiplexers. This method substantially reduces the resource utilization as well as the power consumption of the system. The second proposed method is the design and implementation of the DWT filter banks using IIR filters which employ less number of arithmetic operations compared to the state-of-the-art FIR wavelets. This reduces the hardware complexity of the analysis filter bank of the DWT and can be employed in applications where the reconstruction is not required. However, the synthesis filter bank for the IIR wavelet transform has a higher computational complexity compared to the conventional FIR wavelet synthesis filter banks since re-indexing of the filtered data sequence is required that can only be achieved via the use of extra registers. Therefore, this led to the proposal of a novel design which replaces the complex IIR based synthesis filter banks with FIR fil-ters which are the approximations of the associated IIR filters. Finally, a comparative study is presented where the hybrid IIR/FIR and FIR/FIR wavelet filter banks are de-ployed in a typical noise reduction scenario using the wavelet thresholding techniques. It is concluded that the proposed hybrid IIR/FIR wavelet filter banks provide better denoising performance, reduced computational complexity and power consumption in comparison to their IIR/IIR and FIR/FIR counterparts

Low-Cost Sensors and Biological Signals

Many sensors are currently available at prices lower than USD 100 and cover a wide range of biological signals: motion, muscle activity, heart rate, etc. Such low-cost sensors have metrological features allowing them to be used in everyday life and clinical applications, where gold-standard material is both too expensive and time-consuming to be used. The selected papers present current applications of low-cost sensors in domains such as physiotherapy, rehabilitation, and affective technologies. The results cover various aspects of low-cost sensor technology from hardware design to software optimization

Low power digital baseband core for wireless Micro-Neural-Interface using CMOS sub/near-threshold circuit

This thesis presents the work on designing and implementing a low power digital baseband core with custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) System-on-Chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of distributed sensors, is designed to control the operation of individual MNI and communicate and control MNI devices implanted across the brain using received downlink commands from external base station and store/dump targeted neural data uplink in an energy efficient manner. The application specific protocol defines three modes (Time Stamp Mode, Streaming Mode and Snippet Mode) to extract neural signals with on-chip signal conditioning and discrimination. In Time Stamp Mode, Streaming Mode and Snippet Mode, the core executes basic on-chip spike discrimination and compression, real-time monitoring and segment capturing of neural signals so single spike timing as well as inter-spike timing can be retrieved with high temporal and spatial resolution. To implement the core control logic using sub/near-threshold logic, a novel digital design methodology is proposed which considers INWE (Inverse-Narrow-Width-Effect), RSCE (Reverse-Short-Channel-Effect) and variation comprehensively to size the transistor width and length accordingly to achieve close-to-optimum digital circuits. Ultra-low-power cell library containing 67 cells including physical cells and decoupling capacitor cells using the optimum fingers is designed, laid-out, characterized, and abstracted. A robust on-chip sense-amp-less SRAM memory (8X32 size) for storing neural data is implemented using 8T topology and LVT fingers. The design is validated with silicon tapeout and measurement shows the digital baseband core works at 400mV and 1.28 MHz system clock with an average power consumption of 2.2 μW, resulting in highest reported communication power efficiency of 290Kbps/μW to date

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumption and high energy efficiency have emerged as the two key criteria for embedded microprocessor design. In this thesis we present a range of microarchitectural low-power design techniques which enable the increase of performance for embedded microprocessors and/or the reduction of energy consumption, e.g., through voltage scaling. In the context of cryptographic applications, we explore the effectiveness of instruction set extensions (ISEs) for a range of different cryptographic hash functions (SHA-3 candidates) on a 16-bit microcontroller architecture (PIC24). Specifically, we demonstrate the effectiveness of light-weight ISEs based on lookup table integration and microcoded instructions using finite state machines for operand and address generation. On-node processing in autonomous wireless sensor node devices requires deeply embedded cores with extremely low power consumption. To address this need, we present TamaRISC, a custom-designed ISA with a corresponding ultra-low-power microarchitecture implementation. The TamaRISC architecture is employed in conjunction with an ISE and standard cell memories to design a sub-threshold capable processor system targeted at compressed sensing applications. We furthermore employ TamaRISC in a hybrid SIMD/MIMD multi-core architecture targeted at moderate to high processing requirements (> 1 MOPS). A range of different microarchitectural techniques for efficient memory organization are presented. Specifically, we introduce a configurable data memory mapping technique for private and shared access, as well as instruction broadcast together with synchronized code execution based on checkpointing. We then study an inherent suboptimality due to the worst-case design principle in synchronous circuits, and introduce the concept of dynamic timing margins. We show that dynamic timing margins exist in microprocessor circuits, and that these margins are to a large extent state-dependent and that they are correlated to the sequences of instruction types which are executed within the processor pipeline. To perform this analysis we propose a circuit/processor characterization flow and tool called dynamic timing analysis. Moreover, this flow is employed in order to devise a high-level instruction set simulation environment for impact-evaluation of timing errors on application performance. The presented approach improves the state of the art significantly in terms of simulation accuracy through the use of statistical fault injection. The dynamic timing margins in microprocessors are then systematically exploited for throughput improvements or energy reductions via our proposed instruction-based dynamic clock adjustment (DCA) technique. To this end, we introduce a 6-stage 32-bit microprocessor with cycle-by-cycle DCA. Besides a comprehensive design flow and simulation environment for evaluation of the DCA approach, we additionally present a silicon prototype of a DCA-enabled OpenRISC microarchitecture fabricated in 28 nm FD-SOI CMOS. The test chip includes a suitable clock generation unit which allows for cycle-by-cycle DCA over a wide range with fine granularity at frequencies exceeding 1 GHz. Measurement results of speedups and power reductions are provided

A fully-wearable non-invasive SSVEP-based BCI system enabled by AR techniques for daily use in real environment.

This thesis aims to explore the design and implementation of Brain Computer Interfaces (BCIs) specifically for non medical scenarios, and therefore to propose a solution that overcomes typical drawbacks of existing systems such as long and uncomfortable setup time, scarce or nonexistent mobility, and poor real-time performance. The research starts from the design and implementation of a plug-and-play wearable low-power BCI that is capable of decoding up to eight commands displayed on a LCD screen, with about 2 seconds of latency. The thesis also addresses the issues emerging from the usage of the BCI during a walk in a real environment while tracking the subject via indoor positioning system. Furthermore, the BCI is then enhanced with a smart glasses device that projects the BCI visual interface with augmented reality (AR) techniques, unbinding the system usage from the need of infrastructures in the surrounding environment

Bladder Volume Decoding from Afferent Neural Activity

RÉSUMÉ Lorsque les fonctions de stockage et de miction de la vessie échouent à la suite de traumatismes médullaires, ou en raison d'autres maladies neurologiques, de conditions de santé ou au vieillissement, des complications graves pour la santé du patient se produisent. Actuellement, il est possible de restaurer partiellement les fonctions de la vessie chez les patients réfractaires aux médicaments à l'aide des neurostimulateurs implantables. Pour améliorer l'efficacité et la sécurité de ces neuroprothèses, il faut un capteur de la vessie capable de détecter l’urine stockée afin de mettre en place un système en boucle fermée qui applique la stimulation électrique uniquement lorsque nécessaire. Le capteur peut également servir à aviser les patients ayant des sensations affaiblies pour les aviser en temps opportun le moment où la vessie doit être vidée ou quand un volume résiduel postmictionnel anormalement élevé reste après une miction incomplète. Dans cette thèse, on présente de nouvelles méthodes de mesure, ainsi qu’un processeur de signal numérique dédié pour décoder en temps réel le volume de la vessie à partir des enregistrements neuronaux afférents provenant des récepteurs naturels présents dans la paroi de la vessie. Nos principales contributions sont rapportées dans trois articles de journaux avec comité de lecture. On présente d'abord une revue exhaustive de la littérature comprenant des articles de journaux, des brevets et les livres les plus réputés portant sur l'anatomie, la physiologie et la physiopathologie du tractus urinaire inférieur ainsi que sur la mesure du volume ou la pression de la vessie. Cette étude nous a permis d'identifier les besoins qu'un capteur de la vessie doit satisfaire pour être utilisé dans des applications chroniques telles que celles proposées dans cette thèse. On présente aussi le résultat d’une analyse exhaustive des caractéristiques anatomiques et physiologiques de la vessie que nous avons identifiées d’avoir exercé une influence, ou même d’avoir empêché, la réalisation d'un tel capteur dans des études faites au cours des dernières années. Sur la base de cette étude et de l'évaluation systématique des méthodes de mesure pour la vessie, on a conclu que le principe de mesure le mieux adapté pour la surveillance chronique du volume de la vessie était la détection, la discrimination et le décodage de l'activité neuronale afférente découlant des récepteurs spécialisés du volume (mécanorécepteurs), au sujet desquels certains auteurs ont émis l'hypothèse de leur existence dans la muqueuse interne de la vessie. Ensuite, on présente la méthode de mesure qui permet d'estimer en temps réel le volume de la vessie à partir de l'activité afférente des mécanorécepteurs. Notre méthode a été validée avec les----------ABSTRACT Failure of the storage and voiding functions of the urinary bladder due to spinal cord injury (SCI), neural diseases, health conditions, or aging, causes serious complications in a patient's health. Currently, it is possible to partially restore bladder functions in drug-refractory patients using implantable neurostimulators. Improving the efficacy and safety of these neuroprostheses used for bladder functions restoration requires a bladder sensor (BS) capable of detecting urine volume in real-time to implement a closed-loop system that applies electrical stimulation only when required. The BS can also trigger an early warning to advise patients with impaired sensations when the bladder should be voided or when an abnormally high post-voiding residual volume remains after an incomplete voiding. In this thesis, we present new measurement methods and a dedicated digital signal processor for real-time decoding of the bladder volume through afferent neural signals arising from natural receptors present in the bladder wall. The main contributions of this thesis have been reported in three peer-reviewed journal papers. We first present a comprehensive literature review, including papers, patents and mainstay books of bladder anatomy, physiology, and pathophysiology. This review allowed us to identify the requirements (user needs) that a BS must meet for chronic applications, such as those proposed in this thesis. An exhaustive analysis of the particular anatomical and physiological characteristics of the bladder, which we realized had influenced or prevented the achievement of a BS for monitoring the bladder volume or pressure in past studies, are also presented. Based on this study and on a systematic assessment of the measurement methods published in past years, we determined the best measurement principle for chronic bladder volume monitoring: the detection, discrimination and decoding of the afferent neural activity stemming from specialized volume receptors (mechanoreceptors), on which some authors had hypothesized about its existence in the bladder inner mucosa. Next, we present methods that allows for a real-time estimation of bladder volume through the afferent activity of the bladder mechanoreceptors. Our method was validated with data acquired from anesthetized rats in acute experiments. It was possible to qualitatively estimate three states of bladder fullness in 100% of trials when the recorded afferent activity exhibited a Spearman’s correlation coefficient of 0.6 or better. Furthermore, we could quantitatively estimate the bladder volume, and also its pressure, using time-windows of properly chosen duration. The mea