A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18% THD at 75% full-scale while consuming only 1.8μW power consumption