2 research outputs found
Architectural & circuit level techniques to improve energy efficiency of high speed serial links
High performance computing and communication are two key aspects of all information processing systems. With aggressive scaling of silicon technology enabling integration of a large number of transistors in a small area, managing power and thermal reliability has become very challenging. While lowering the power needed for performing computation has been the prime focus for decades, energy consumed for data transfer has recently become a major bottleneck especially in high performance applications. The focus of this thesis is on improving energy efficiency of communication links by exploring design techniques at both the architectural and circuit levels.
In the first part of this work, we propose a time-based equalization scheme to implement transmit de-emphasis in voltage-mode output drivers. Using two-level pulse-width modulation, it overcomes the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers. A prototype PWM-based 5Gb/s voltage-mode transmitter was implemented in a 90nm CMOS process and characterized across different channels and output swings to demonstrate the effectiveness of proposed techniques. The horizontal/vertical eye openings (BER=) at the ends of 60inch and 96inch stripline channels are 78mV/0.6UI and 8mV/0.3UI, respectively. This transmitter achieves an energy efficiency of 3.1mW/Gb/s while compensating for 16-28dB channel loss, which compares favorably with the state-of-the-art.
In the second part, techniques to improve energy efficiency of a complete transceiver are presented. The transmitter employs a novel partially segmented voltage-mode output driver to lower power consumption in pre-drivers during 2-tap FIR equalization. The receiver implements a low power half-rate clock and data recovery with the proposed ring PLL based multi-phase sampling clock generation in CDR loop and charge-based sampling and deserialization. These techniques are verified using the measured results obtained from a 14Gb/s transceiver prototype. Transmitter achieves an energy efficiency of 0.89mW/Gb/s while securing a 0.36UI sampling time margin with at the end of the channel with 11dB loss at Nyquist frequency. The receiver recovers sampling clock with 1.8 long term absolute jitter while recovering 14Gb/s data at . The receiver achieves an energy efficiency of 1.69mW/Gb/s. Transmitter and receiver share an LC PLL, which achieves 0.605 integrated jitter at 7GHz output with an energy efficiency of 0.5mW/GHz. The transceiver as a whole achieves an energy efficiency of 2.8mW/Gb/s