Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator

A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL)

Frequency synthesizers have become a crucial building block in the evolution of modern communication systems and consumer electronics. The spectral purity performance of frequency synthesizers limits the achievable data-rate and presents a noise-power tradeoff. For communication standards such as LTE where the channel spacing is a few kHz, the synthesizers must provide high frequencies with sufficiently wide frequency tuning range and fine frequency resolutions. Such stringent performance must be met with a limited power and small chip area. In this thesis a wideband fractional-N frequency synthesizer based on a subsampling phase locked loop (SSPLL) is presented. The proposed synthesizer which has a frequency resolution less than 100Hz employs a digital fractional controller (DFC) and a 10-bit digital-to-time converter (DTC) to delay the rising edges of the reference clock to achieve fractional phase lock. For fast convergence of the delay calibration, a novel two-step delay correlation loop (DCL) is employed. Furthermore, to provide optimum settling and jitter performance, the loop transfer characteristics during frequency acquisition and phase-lock are decoupled using a dual input loop filter (DILF). The fractional-N sub-sampling PLL (FNSSPLL) is implemented in a TSMC 40nm CMOS technology and occupies a total active area of 0.41mm^2. The PLL operates over frequency range of 2.8 GHz to 4.3 GHz (42% tuning range) while consuming 9.18mW from a 1.1V supply. The integrated jitter performance is better than 390 fs across all fractional frequency channel. The worst case fractional spur of -48.3 dBc occurs at a 650 kHz offset for a 3.75GHz fractional channel. The in-band phase noise measured at a 200 kHz offset is -112.5 dBc/Hz

Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

Digital enhancement techniques for fractional-N frequency synthesizers

Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs. Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs. In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed dynamically to optimize for performance or power dissipation using a dynamic frequency scaling (DFS) technique. Fast frequency switching is highly desirable as long as it does not interrupt code execution; therefore it requires smooth frequency transitions with no undershoots. The second main requirement in processor clocking is the capability of spread spectrum frequency modulation. By spreading the clock energy across a wide bandwidth, the electromagnetic interference (EMI) is dramatically reduced. A conventional PLL clock generation approach suffers from a slow frequency settling and limited spread spectrum modulation capabilities. The proposed open loop fractional divider architecture overcomes the bandwidth limitation in fractional-N PLLs. The fractional divider switches the output frequency instantaneously and provides an excellent spread spectrum performance, where precise and programmable modulation depth and frequency can be applied to satisfy different EMI requirements. The fractional divider has unlimited modulation bandwidth resulting in spread spectrum modulation with no filtering, unlike fractional-N PLL; consequently it achieves higher EMI reduction. A prototype fractional divider was implemented in a 65nm CMOS process, where the measured peak-to-peak jitter is less than 27ps over a wide frequency range from 20MHz to 1GHz. The total power consumption is about 3.2mW for 1GHz output frequency. The all-digital implementation of the divider occupies the smallest area of 0.017mm2 compared to state-of-the-art designs. As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the PLL coupled noise bandwidth trade-off, which imposes stringent noise requirements on the oscillator and/or loop components. Alternatively, an injection-locked clock multiplier (ILCM) provides many advantages in terms of phase noise, power, and area compared to classical PLLs, but they suffer from a narrow lock-in range and a high sensitivity to PVT variations especially at a large multiplication factor (N). In the fourth part of this thesis, a low-jitter, low-power LC-based ILCM with a digital frequency-tracking loop (FTL) is presented. The proposed FTL relies on a new pulse gating technique to continuously tune the oscillator's free-running frequency. The FTL ensures robust operation across PVT variations and resolves the race condition existing in injection locked PLLs by decoupling frequency tuning from the injection path. As a result, the phase locking condition is only determined by the injection path. This work also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25mm2. The prototype ILCM multiplies the reference frequency by 64 to generate an output clock in the range of 6.75GHz-8.25GHz. A superior jitter performance of 190fsrms is achieved, while consuming only 2.25mW power. This translates to a best FoM of -251dB. Unlike conventional PLLs, ILCMs have been fundamentally limited to only integer-N operation and cannot synthesize fractional-N frequencies. In the last part of this thesis, we extend the merits of ILCMs to fractional-N and overcome this fundamental limitation. We employ DTC-based QNC techniques in order to align injected pulses to the oscillator's zero crossings, which enables it to pull the oscillator toward phase lock, thus realizing a fractional-N ILCM. Fabricated in 65nm CMOS process, a prototype 20-bit fractional-N ILCM with an output range of 6.75GHz-8.25GHz consumes only 3.25mW. It achieves excellent jitter performance of 110fsrms and 175fsrms in integer- and fractional-N modes respectively, which translates to the best-reported FoM in both integer- (-255dB) and fractional-N (-252dB) modes. The proposed fractional-N ILCM also features the first-reported rapid on/off capability, where the transient absolute jitter performance at wake-up is bounded below 4ps after less than 4ns. This demonstrates almost instantaneous phase settling. This unique capability enables tremendous energy saving by turning on the clock multiplier only when needed. This energy proportional operation leverages idle times to save power at the system-level of wireline and wireless transceivers

Design of Low-Power Short-Distance Transceiver for Wireless Sensor Networks

Ph.DDOCTOR OF PHILOSOPH

Design of high performance frequency synthesizers in communication systems

Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption

Design of a Dual Band Local Positioning System

This work presents a robust dual band local positioning system (LPS) working in the 2.4GHz and 5.8GHz industrial science medical (ISM) bands. Position measurement is based on the frequency-modulated continuous wave (FMCW) radar approach, which uses radio frequency (RF) chirp signals for propagation time and therefore distance measurements. Contrary to state of the art LPS, the presented system uses data from both bands to improve accuracy, precision and robustness. A complete system prototype is designed consisting of base stations and tags encapsulating most of the RF and analogue signal processing in custom integrated circuits. This design approach allows to reduce size and power consumption compared to a hybrid system using off-the-shelf components. Key components are implemented using concepts, which support operation in multiple frequency bands, namely, the receiver consisting of a low noise amplifier (LNA), mixer, frequency synthesizer with a wide band voltage-controlled oscillator (VCO) having broadband chirp generation capabilities and a dual band power amplifier. System imperfections occurring in FMCW radar systems are modelled. Effects neglected in literature such as compression, intermodulation, the influence of automatic gain control, blockers and spurious emissions are modeled. The results are used to derive a specification set for the circuit design. Position estimation from measured distances is done using an enhanced version of the grid search algorithm, which makes use of data from multiple frequency bands. The algorithm is designed to be easily and efficiently implemented in embedded systems. Measurements show a coverage range of the system of at least 245m. Ranging accuracy in an outdoor scenario can be as low as 8.2cm. Comparative dual band position measurements prove an effective outlier filtering in indoor and outdoor scenarios compared to single band results, yielding in a large gain of accuracy. Positioning accuracy in an indoor scenario with an area of 276m² can be improved from 1.27m at 2.4GHz and 1.86m at 5.8GHz to only 0.38m in the dual band case, corresponding to an improvement by at least a factor of 3.3. In a large outdoor scenario of 4.8 km², accuracy improves from 1.88m at 2.4GHz and 5.93m at 5.8GHz to 0.68m with dual band processing, which is a factor of at least 2.8.Die vorliegende Arbeit befasst sich mit dem Entwurf eines robusten lokalen Positionierungssystems (LPS), welches in den lizenzfreien Frequenzbereichen für industrielle, wissenschaftliche und medizinische Zwecke (industrial, scientific, medical, ISM) bei 2,4GHz und 5,8GHz arbeitet. Die Positionsbestimmung beruht auf dem Prinzip des frequenzmodulierten Dauerstrichradars (frequency modulated continuous wave, FMCW-Radar), welches hochfrequente Rampensignale für Laufzeitmessungen und damit Abstandsmessungen benutzt. Im Gegensatz zu aktuellen Arbeiten auf diesem Gebiet benutzt das vorgestellte System Daten aus beiden Frequenzbändern zur Erhöhung der Genauigkeit und Präzision sowie Verbesserung der Robustheit. Ein Prototyp des kompletten Systems bestehend aus Basisstationen und mobilen Stationen wurde entworfen. Fast die gesamte analoge hochfrequente Signalverarbeitungskette wurde als anwendungsspezifische integrierte Schaltung realisiert. Verglichen mit Systemen aus Standardkomponenten erlaubt dieser Ansatz die Miniaturisierung der Systemkomponenten und die Einsparung von Leistung. Schlüsselkomponenten wurden mit Konzepten für mehrbandige oder breitbandige Schaltungen entworfen. Dabei wurden Sender und Empfänger bestehend aus rauscharmem Verstärker, Mischer und Frequenzsynthesizer mit breitbandiger Frequenzrampenfunktion implementiert. Außerdem wurde ein Leistungsverstärker für die gleichzeitige Nutzung der beiden definierten Frequenzbänder entworfen. Um Spezifikationen für den Schaltungsentwurf zu erhalten, wurden in der Fachliteratur vernachlässigte Nichtidealitäten von FMCW-Radarsystemen modelliert. Dazu gehören Signalverzerrungen durch Kompression oder Intermodulation, der Einfluss der automatischen Verstärkungseinstellung sowie schmalbandige Störer und Nebenschwingungen. Die Ergebnisse der Modellierung wurden benutzt, um eine Spezifikation für den Schaltungsentwurf zu erhalten. Die Schätzung der Position aus gemessenen Abständen wurde über eine erweiterte Version des Gittersuchalgorithmus erreicht. Dieser nutzt die Abstandsmessdaten aus beiden Frequenzbändern. Der Algorithmus ist so entworfen, dass er effizient in einem eingebetteten System implementiert werden kann. Messungen zeigen eine maximale Reichweite des Systems von mindestens 245m. Die Genauigkeit von Abstandsmessungen im Freiland beträgt 8,2cm. Positionsmessungen wurden unter Verwendung beider Einzelbänder durchgeführt und mit den Ergebnissen des Zweiband-Gittersuchalgorithmus verglichen. Damit konnte eine starke Verbesserung der Positionsgenauigkeit erreicht werden. Die Genauigkeit in einem Innenraum mit einer Grundfläche von 276m² kann verbessert werden von 1,27m bei 2,4GHz und 1,86m bei 5,8GHz zu nur 0,38m im Zweibandverfahren. Das entspricht einer Verbesserung um einen Faktor von mindestens 3,3. In einem größeren Außenszenario mit einer Fläche von 4,8 km² verbessert sich die Genauigkeit um einen Faktor von mindestens 2,8 von 1,88m bei 2,4GHz und 5,93m bei 5,8GHz auf 0,68m bei Nutzung von Daten aus beiden Frequenzbändern

Design of Fully-Integrated High-Resolution Radars in CMOS and BiCMOS Technologies

The RADAR, acronym that stands for RAdio Detection And ranging, is a device that uses electromagnetic waves to detect the presence and the distance of an illuminated target. The idea of such a system was presented in the early 1900s to determine the presence of ships. Later on, with the approach of World War II, the radar gained the interest of the army who decided to use it for defense purposes, in order to detect the presence, the distance and the speed of ships, planes and even tanks. Nowadays, the use of similar systems is extended outside the military area. Common applications span from weather surveillance to Earth composition mapping and from flight control to vehicle speed monitoring. Moreover, the introduction of new ultrawideband (UWB) technologies makes it possible to perform radar imaging which can be successfully used in the automotive or medical field. The existence of a plenty of known applications is the reason behind the choice of the topic of this thesis, which is the design of fully-integrated high-resolution radars. The first part of this work gives a brief introduction on high resolution radars and describes its working principle in a mathematical way. Then it gives a comparison between the existing radar types and motivates the choice of an integrated solution instead of a discrete one. The second part concerns the analysis and design of two CMOS high-resolution radar prototypes tailored for the early detection of the breast cancer. This part begins with an explanation of the motivations behind this project. Then it gives a thorough system analysis which indicates the best radar architecture in presence of impairments and dictates all the electrical system specifications. Afterwards, it describes in depth each block of the transceivers with particular emphasis on the local oscillator (LO) generation system which is the most critical block of the designs. Finally, the last section of this part presents the measurement results. In particular, it shows that the designed radar operates over 3 octaves from 2 to 16GHz, has a conversion gain of 36dB, a flicker-noise-corner of 30Hz and a dynamic range of 107dB. These characteristics turn into a resolution of 3mm inside the body, more than enough to detect even the smallest tumor. The third and last part of this thesis focuses on the analysis and design of some important building blocks for phased-array radars, including phase shifter (PHS), true time delay (TTD) and power combiner. This part begins with an exhaustive introduction on phased array systems followed by a detailed description of each proposed lumped-element block. The main features of each block is the very low insertion loss, the wideband characteristic and the low area consumption. Finally, the major effects of circuit parasitics are described followed by simulation and measurement results

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented