31 research outputs found
Time-Domain/Digital Frequency Synchronized Hysteresis Based Fully Integrated Voltage Regulator
abstract: Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion
The purpose of this thesis is the proposal and implementation of data conversion
open-loop architectures based on voltage-controlled oscillators (VCOs) built with
ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to
the newest complementary metal-oxide-semiconductor (CMOS) nodes.
The scaling of the design technologies into the nanometer range imposes the
reduction of the supply voltage towards small and power-efficient architectures,
leading to lower voltage overhead of the transistors. Additionally, phenomena
like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between
devices and PVT variations) make the design of classic structures for ADCs more
challenging. In recent years, time-encoded A/D conversion has gained relevant
popularity due to the possibility of being implemented with mostly digital structures.
Within this trend, VCOs designed with ring oscillator based topologies
have emerged as promising candidates for the conception of new digitization
techniques.
RO-based data converters show excellent scalability and sensitivity, apart from
some other desirable properties, such as inherent quantization noise shaping and
implicit anti-aliasing filtering. However, their nonlinearity and the limited time
delay achievable in a simple NOT gate drastically limits the resolution of the converter,
especially if we focus on wide-band A/D conversion. This thesis proposes
new ways to alleviate these issues.
Firstly, circuit-based techniques to compensate for the nonlinearity of the ring
oscillator are proposed and compared to equivalent state-of-the-art solutions.
The proposals are designed and simulated in a 65-nm CMOS node for open-loop
RO-based ADC architectures. One of the techniques is also validated experimentally
through a prototype. Secondly, new ways to artificially increase the effective
oscillation frequency are introduced and validated by simulations. Finally, new
approaches to shape the quantization noise and filter the output spectrum of a
RO-based ADC are proposed theoretically. In particular, a quadrature RO-based
band-pass ADC and a power-efficient Nyquist A/D converter are proposed and
validated by simulations.
All the techniques proposed in this work are especially devoted for highbandwidth
applications, such as Internet-of-Things (IoT) nodes or maximally
digital radio receivers. Nevertheless, their field of application is not restricted to
them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas
de conversión de datos basadas en osciladores en anillos, compatibles
con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación
más modernos donde las estructuras digitales se ven favorecidas.
La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción
de la tensión de alimentación para el desarrollo de arquitecturas pequeñas
y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión
para saturar transistores, lo que añadido a una ganancia cada vez menor
de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones
de proceso, tensión y temperatura han llevado a que sea cada vez más complejo
el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión
A/D basada en codificación temporal ha ganado gran popularidad dado
que permite la implementación de estructuras mayoritariamente digitales. Como
parte de esta evolución, los osciladores controlados por tensión diseñados con topologías
de oscilador en anillo han surgido como un candidato prometedor para
la concepción de nuevas técnicas de digitalización.
Los convertidores de datos basados en osciladores en anillo son extremadamente
sensibles (variación de frecuencia con respecto a la señal de entrada) así como
escalables, además de otras propiedades muy atractivas, como el conformado
espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su
respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta
NOT restringen la resolución del conversor, especialmente para conversión A/D
en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas
técnicas para aliviar este tipo de problemas.
En primer lugar, se proponen técnicas basadas en circuito para compensar el
efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones
equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología
CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas
presentadas es también validada experimentalmente a través de un prototipo.
En segundo lugar, se introducen y validan por simulación varias formas de incrementar
artificialmente la frecuencia de oscilación efectiva. Para finalizar, se
proponen teóricamente dos enfoques para configurar nuevas formas de conformación
del ruido de cuantificación y filtrado del espectro de salida de los datos
digitales. En particular, son propuestos y validados por simulación un ADC pasobanda
en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente
para aplicaciones de alto ancho de banda, tales como módulos para el Internet
de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar
de ello, son extrapolables también a otros campos como el de la instrumentación
biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí
Interface Circuits for Microsensor Integrated Systems
ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.
e health iot universe a review
The Internet of Things (IoT) devices are able to collect and share data directly with other devices through the cloud environment, providing a huge amount of information to be gathered, stored and analyzed for data-analytics processes. The scenarios in which the IoT devices may be useful are amazing varying, from automotive, to industrial automation or remote monitoring of domestic environment. Furthermore, has been proved that healthcare applications represent an important field of interest for IoT devices, due to the capability of improving the access to care, reducing the cost of healthcare and most importantly increasing the quality of life of the patients. In this paper, we analyze the state-of-art of IoT in medical environment, illustrating an extended range of IoT-driven healthcare applications that, however, still need innovative and high technology-based solutions to be considered ready to market. In particular, problems regarding characteristics of response-time and precision will be examined. Furthermore, wearable and energy saving properties will be investigated in this paper and also the IT architectures able to ensure security and privacy during the all data-transmission process. Finally, considerations about data mining applications, such as risks prediction, classification and clustering will be provided, that are considered fundamental issues to ensure the accuracy of the care processes
Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology
Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning
applications has increased the demand of MEMS-based digital microphones.
Mobile devices have several microphones enabling noise canceling, acoustic beamforming
and speech recognition. With the development of machine learning applications
the interest to integrate sensors with neural networks has increased.
This has driven the interest to develop digital microphones in nanometer CMOS
nodes where the microphone analog-front end and digital processing, potentially
including neural networks, is integrated on the same chip.
Traditionally, analog-to-digital converters (ADCs) in digital microphones have
been implemented using high order Sigma-Delta modulators. The most common
technique to implement these high order Sigma-Selta modulators is switchedcapacitor
CMOS circuits. Recently, to reduce power consumption and make them
more suitable for tasks that require always-on operation, such as keyword recognition,
switched-capacitor circuits have been improved using inverter-based operational
amplifier integrators. Alternatively, switched-capacitor based Sigma-
Delta modulators have been replaced by continuous time Sigma-Delta converters.
Nevertheless, in both implementations the input signal is voltage encoded
across the modulator, making the integration in smaller CMOS nodes more challenging
due to the reduced voltage supply.
An alternative technique consists on encoding the input signal on time (or
frequency) instead of voltage. This is what time-encoded converters do. Lately,
time-encoding converters have gained popularity as they are more suitable to
nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have
drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs).
VCO-ADCs can be implemented using CMOS inverter based ring oscillators
(RO) and digital circuitry. They also show noise-shaping properties.
This makes them a very interesting alternative for implementation of ADCs in
nanometer CMOS nodes. Nevertheless, two main circuit impairments are present
in VCO-ADCs, and both come from the oscillator non-idealities. The first of them
is the oscillator phase noise, that reduces the resolution of the ADC. The second
is the non-linear tuning curve of the oscillator, that results in harmonic distortion
at medium to high input amplitudes.
In this thesis we analyze the use of time encoding ADCs for MEMS microphones
with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we
study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in
sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations
for the noise transfer function (NTF) of a third order sigma-delta using a second
order filter and the NSQ are presented.
Secondly, we move our attention to the topic of RO-ADCs. We present a high
dynamic range MEMS microphone 130nm CMOS chip based on an open-loop
VCO-ADC. This dissertation shows the implementation of the analog front-end
that includes the oscillator and the MEMS interface, with a focus on achieving
low power consumption with low noise and a high dynamic range. The digital
circuitry is left to be explained by the coauthor of the chip in his dissertation. The
chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5%
at 128 dBSPL with a power consumption of 438μW.
After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement
an unsampled feedback loop around the oscillator. The objective is to reduce
distortion. Additionally phase noise mitigation is achieved. A first topology
including an operational amplifier to increase the loop gain is analyzed. The design
is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR
with an analog power consumption of 600μW. A second topology without the
operational amplifier is also analyzed. Two chips are designed with this topology.
The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto-
digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a
power consumption of 482μW. The second chip includes only the oscillator and
is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog
power consumption is 153μW.
To finish this thesis, two circuits that use an FDR with a ring oscillator are
presented. The first is a capacity-to-digital converter (CDC). The second is a filter
made with an FDR and an oscillator intended for voice activity detection tasks
(VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de
machine-learning han aumentado la demanda de micrófonos digitales basados
en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación
de ruido, el beamforming o conformación de haces y el reconocimiento
de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés
por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el
interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde
el front-end analógico y el procesamiento digital del micrófono, que puede
incluir redes neuronales, está integrado en el mismo chip.
Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos
digitales han sido implementados utilizando moduladores Sigma-Delta de
orden elevado. La técnica más común para implementar estos moduladores Sigma-
Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente,
para reducir el consumo de potencia y hacerlos más adecuados para las tareas que
requieren una operación continua, como el reconocimiento de palabras clave, los
convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con
el uso de integradores implementados con amplificadores operacionales basados
en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas
han sido reemplazados por moduladores en tiempo continuo. No obstante,
en ambas implementaciones, la señal de entrada es codificada en voltaje durante
el proceso de conversión, lo que hace que la integración en nodos CMOS más
pequeños sea complicada debido a la menor tensión de alimentación.
Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o
frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación
temporal. Recientemente, los convertidores de codificación temporal
han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos
que los convertidores Sigma-Delta. Entre los que más interés han despertado
encontramos los ADCs basados en osciladores controlados por tensión
(VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo
(RO) implementados con inversores CMOS y circuitos digitales. Esta familia
de convertidores también tiene conformado de ruido. Esto los convierte en una
alternativa muy interesante para la implementación de convertidores en nodos
CMOS nanométricos. Sin embargo, dos problemas principales están presentes en
este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero
de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no
lineal del oscilador, lo que causa distorsión a amplitudes medias y altas.
En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos
MEMS, con especial interés en ADCS basados en osciladores de anillo
(RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado
de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador
agrega un orden adicional de conformado de ruido al modulador, mejorando la
resolución. En este documento se explica el cuantificador y obtienen las ecuaciones
para la función de transferencia de ruido (NTF) de un sigma-delta de tercer
orden usando un filtro de segundo orden y el NSQ.
En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos
el chip de un micrófono MEMS de alto rango dinámico en CMOS de
130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación
del front-end analógico que incluye el oscilador y la interfaz con
el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un
bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La
descripción del back-end digital se deja para la tesis del couator del chip. La
SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD
de 1,5% a 128 dBSPL y un consumo de potencia de 438μW.
Finalmente, se analiza el uso de una resistencia dependiente de frecuencia
(FDR) para implementar un bucle de realimentación no muestreado alrededor
del oscilador. El objetivo es reducir la distorsión. Además, también se logra la
mitigación del ruido de fase del oscilador. Se analyza una primera topologia de
realimentación incluyendo un amplificador operacional para incrementar la ganancia
de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que
logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la
parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador
operacional. Se fabrican y miden dos chips diseñados con esta topologia.
El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye
el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de
76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador
y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el
el consumo de potencia analógica es de 153μW.
Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador
en anillo. El primero es un convertidor de capacidad a digital (CDC). El
segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de
detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout
RF MEMS reference oscillators platform for wireless communications
A complete platform for RF MEMS reference oscillator is built to replace bulky quartz from mobile devices, thus reducing size and cost. The design targets LTE transceivers. A low phase noise 76.8 MHz reference oscillator is designed using material temperature compensated AlN-on-silicon resonator. The thesis proposes a system combining piezoelectric resonator with low loading CMOS cross coupled series resonance oscillator to reach state-of-the-art LTE phase noise specifications. The designed resonator is a two port fundamental width extensional mode resonator. The resonator characterized by high unloaded quality factor in vacuum is designed with low temperature coefficient of frequency (TCF) using as compensation material which enhances the TCF from - 3000 ppm to 105 ppm across temperature ranges of -40˚C to 85˚C. By using a series resonant CMOS oscillator, phase noise of -123 dBc/Hz at 1 kHz, and -162 dBc/Hz at 1MHz offset is achieved. The oscillator’s integrated RMS jitter is 106 fs (10 kHz–20 MHz), consuming 850 μA, with startup time is 250μs, achieving a Figure-of-merit (FOM) of 216 dB. Electronic frequency compensation is presented to further enhance the frequency stability of the oscillator. Initial frequency offset of 8000 ppm and temperature drift errors are combined and further addressed electronically. A simple digital compensation circuitry generates a compensation word as an input to 21 bit MASH 1 -1-1 sigma delta modulator incorporated in RF LTE fractional N-PLL for frequency compensation. Temperature is sensed using low power BJT band-gap front end circuitry with 12 bit temperature to digital converter characterized by a resolution of 0.075˚C. The smart temperature sensor consumes only 4.6 μA. 700 MHz band LTE signal proved to have the stringent phase noise and frequency resolution specifications among all LTE bands. For this band, the achieved jitter value is 1.29 ps and the output frequency stability is 0.5 ppm over temperature ranges from -40˚C to 85˚C. The system is built on 32nm CMOS technology using 1.8V IO device
Design of Power Management Integrated Circuits and High-Performance ADCs
A battery-powered system has widely expanded its applications to implantable medical devices
(IMDs) and portable electronic devices. Since portable devices or IMDs operate in the
energy-constrained environment, their low-power operations in combination with efficiently sourcing
energy to them are key problems to extend device life. This research proposes novel circuit
techniques for two essential functions of a power receiving unit (PRU) in the energy-constrained
environment, which are power management and signal processing.
The first part of this dissertation discusses power management integrated circuits for a PRU.
From a power management perspective, the most critical two circuit blocks are a front-end rectifier
and a battery charger. The front-end CMOS active rectifier converts transmitted AC power into
DC power. High power conversion efficiency (PCE) is required to reduce power loss during the
power transfer, and high voltage conversion ratio (VCR) is required for the rectifier to enable low-voltage
operations. The proposed 13.56-MHz CMOS active rectifier presents low-power circuit
techniques for comparators and controllers to reduce increasing power loss of an active diode with
offset/delay calibration. It is implemented with 5-V devices of a 0.35 µm CMOS process to support
high voltage. A peak PCE of 89.0%, a peak VCR of 90.1%, and a maximum output power of 126.7
mW are measured for 200Ω loading.
The linear battery charger stores the converted DC power into a battery. Since even small
power saving can be enough to run the low-power PRU, a battery charger with low IvQ is desirable.
The presented battery charger is based on a single amplifier for regulation and the charging
phase transition from the constant-current (CC) phase to the constant-voltage (CV) phase. The
proposed unified amplifier is based on stacked differential pairs which share the bias current. Its
current-steering property removes multiple amplifiers for regulation and the CC-CV transition, and
achieves high unity-gain loop bandwidth for fast regulation. The charger with the maximum charging
current of 25 mA is implemented in 0.35 µm CMOS. A peak charger efficiency of 94% and
average charger efficiency of 88% are achieved with an 80-mAh Li-ion polymer battery.
The second part of this dissertation focuses on analog-to-digital converters (ADCs). From a
signal processing perspective, an ADC is one of the most important circuit blocks in the PRU.
Hence, an energy-efficient ADC is essential in the energy-constrained environment. A pipelined successive
approximation register (SAR) ADC has good energy efficiency in a design space of
moderate-to-high speeds and resolutions. Process-Voltage-Temperature variations of a dynamic
amplifier in the pipelined-SAR ADC is a key design issue. This research presents two dynamic
amplifier architectures for temperature compensation. One is based on a voltage-to-time converter
(VTC) and a time-to-voltage converter (TVC), and the other is based on a temperature-dependent
common-mode detector. The former amplifier is adopted in a 13-bit 10-50 MS/s subranging
pipelined-SAR ADC fabricated in 0.13-µm CMOS. The ADC can operate under the power supply
voltage of 0.8-1.2 V. Figure-of-Merits (FoMs) of 4-11.3 fJ/conversion-step are achieved. The latter
amplifier is also implemented in 0.13-µm CMOS, consuming 0.11 mW at 50 MS/s. Its measured
gain variation is 2.1% across the temperature range of -20°C to 85 °C