Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

Interface Circuits for Microsensor Integrated Systems

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.

Energy-Efficient Time-Based Encoders and Digital Signal Processors in Continuous Time

Continuous-time (CT) data conversion and continuous-time digital signal processing (DSP) are an interesting alternative to conventional methods of signal conversion and processing. This alternative proposes time-based encoding that may not suffer from aliasing; shows superior spectral properties (e.g. no quantization noise floor); and enables time-based, event-driven, flexible signal processing using digital circuits, thus scaling well with technology. Despite these interesting features, this approach has so far been limited by the CT encoder, due to both its relatively poor energy efficiency and the constraints it imposes on the subsequent CT DSP. In this thesis, we present three principles that address these limitations and help improve the CT ADC/DSP system. First, an adaptive-resolution encoding scheme that achieves first-order reconstruction with simple circuitry is proposed. It is shown that for certain signals, the scheme can significantly reduce the number of samples generated per unit of time for a given accuracy compared to schemes based on zero-order-hold reconstruction, thus promising to lead to low dynamic power dissipation at the system level. Presented next is a novel time-based CT ADC architecture, and associated encoding scheme, that allows a compact, energy-efficient circuit implementation, and achieves first-order quantization error spectral shaping. The design of a test chip, implemented in a 0.65-V 28-nm FDSOI process, that includes this CT ADC and a 10-tap programmable FIR CT DSP to process its output is described. The system achieves 32 dB – 42 dB SNDR over a 10 MHz – 50 MHz bandwidth, occupies 0.093 mm2, and dissipates 15 µW–163 µW as the input amplitude goes from zero to full scale. Finally, an investigation into the possibility of CT encoding using voltage-controlled oscillators is undertaken, and it leads to a CT ADC/DSP system architecture composed primarily of asynchronous digital delays. The latter makes the system highly digital and technology-scaling-friendly and, hence, is particularly attractive from the point of view of technology migration. The design of a test chip, where this delay-based CT ADC/DSP system architecture is used to implement a 16-tap programmable FIR filter, in a 1.2-V 28-nm FDSOI process, is described. Simulations show that the system will achieve a 33 dB – 40 dB SNDR over a 600 MHz bandwidth, while dissipating 4 mW

Ultra Low Power FM-UWB Transceiver for High-Density Wireless Sensor Networks

The WiseSkin project aims to provide a non-invasive solution for restoration of a natural sense of touch to persons using prosthetic limbs. By embedding sensor nodes into the silicone coating of the prosthesis, which acts as a sensory skin, WiseSkin targets to provide improved gripping, manipulation and mobility for amputees. Flexibility, freedom of movement and comfort demand unobtrusive, highly miniaturized, low-power sensing capabilities built into the artificial skin, which is then integrated with a sensory feedback system. Wireless communication between the sensor nodes provides more flexibility, better scalability and robustness compared to wired solution, and is therefore a preferred approach for WiseSkin. Design of an RF transceiver tailored for the specific needs of WiseSkin is the topic of this work. The properties of FM ultra-wide band (FM-UWB) modulation make it a good candidate for High-Density Wireless Sensor Networks (HD-WSN). The proposed FM-UWB receivers take advantage of short range to reduce power consumption, and exploit robustness of this wideband modulation scheme. The LNA, identified as the biggest consumer, is removed and signal is directly converted to dc, where amplification and demodulation are performed. Owing to 500 MHz bandwidth, frequency offset and phase noise can be tolerated, and a low-power, free-running ring oscillator can be used to generate the LO signal. The receiver is referred to as an approximate zero-IF receiver. Two receiver architectures are studied. The first one performs quadrature downconversion, and owing to the demodulator linearity, provides the multi-user capability. In the second receiver, quadrature demodulation is replaced by the single-ended one. Due to the nature of the demodulator, sensitivity degrades, and multiple FM-UWB signals cannot be resolved, but the consumption is almost halved compared to the first receiver. The proposed approach is verified through two integrations, both in a standard 65 nm bulk CMOS process. In the first run, a standalone quadrature receiver was integrated. Power consumption of 423 uW was measured, while achieving -70 dBm sensitivity. Good narrow-band interference rejection and multiuser capability with up to 4 FM-UWB channels could be achieved. In the second run, a full transceiver is integrated, with both quadrature and single-ended receivers and a transmitter, all sharing a single IO pad, without the need for any external passive components or switches. The quadrature receiver, with on-chip baseband processing and multi-user support, in this case consumes 550 uW, with a sesensitivity of -68 dBm. The low power receiver consumes 267 uW, and provides -57 dBm sensitivity, at a single FM-UWB channel. The implemented trantransmitter transmits a 100 kb/s FM-UWB signal at -11.4 dBm, while drawing 583 uW from the 1 V supply. The on-chip clock recovery allows reference frequency offset up to 8000 ppm. Since state of the art on-chip RC oscillators can provide below 2100 ppm across the temperature range of interest, the implemented transceiver demonstrates the feasibility of a fully integrated FM-UWB radio with no need for a quartz reference or any external components. In addition, the transceiver can tolerate up to 3 dBm narrow-band interferer at 2.4 GHz. Such a strong signal can be used to remotely power the sensor nodes inside the artificial skin and enable a truly wirelessWiseSkin solution

Advances in Filter Miniaturization and Design/Analysis of RF MEMS Tunable Filters

The main purpose of this dissertation was to address key issues in the design and analysis of RF/microwave filters for wireless applications. Since RF/microwave filters are one of the bulkiest parts of communication systems, their miniaturization is one of the most important technological challenges for the development of compact transceivers. In this work, novel miniaturization techniques were investigated for single-band, dual-band, ultra-wideband and tunable bandpass filters. In single-band filters, the use of cross-shaped fractals in half-mode substrate-integrated-waveguide bandpass filters resulted in a 37 percent size reduction. A compact bandpass filter that occupies an area of 0.315 mm2 is implemented in 90-nm CMOS technology for 20 GHz applications. For dual-band filters, using half-mode substrate-integrated-waveguides resulted in a filter that is six times smaller than its full-mode counterpart. For ultra-wideband filters, using slow-wave capacitively-loaded coplanar-waveguides resulted in a filter with improved stopband performance and frequency notch, while being 25 percent smaller in size. A major part of this work also dealt with the concept of 'hybrid' RF MEMS tunable filters where packaged, off-the-shelf RF MEMS switches were used to implement high-performance tunable filters using substrate-integrated-waveguide technology. These 'hybrid' filters are very easily fabricated compared to current state-of-the-art RF MEMS tunable filters because they do not require a clean-room facility. Both the full-mode and half-mode substrate-integrated waveguide tunable filters reported in this work have the best Q-factors (93 - 132 and 75 - 140, respectively) compared to any 'hybrid' RF MEMS tunable filter reported in current literature. Also, the half-mode substrate-integrated waveguide tunable filter is 2.5 times smaller than its full-mode counterpart while having similar performance. This dissertation also presented detailed analytical and simulation-based studies of nonlinear noise phenomena induced by Brownian motion in all-pole RF MEMS tunable filters. Two independent mathematical methods are proposed to calculate phase noise in RF MEMS tunable filters: (1) pole-perturbation approach, and (2) admittance-approach. These methods are compared to each other and to harmonic balance noise simulations using the CAD-model of the RF MEMS switch. To account for the switch nonlinearity in the mathematical methods, a nonlinear nodal analysis technique for tunable filters is also presented. In summary, it is shown that output signal-to-noise ratio degradation due to Brownian motion is maximum for low fractional bandwidth, high order and high quality factor RF MEMS tunable filters. Finally, a self-sustained microwave platform to detect the dielectric constant of organic liquids is presented in this dissertation. The main idea is to use a voltage- controlled negative-resistance oscillator whose frequency of oscillation varies according to the organic liquid under test. To make the system self-sustained, the oscillator is embedded in a frequency synthesizer system, which is then digitally interfaced to a computer for calculation of dielectric constant. Such a system has potential uses in a variety of applications in medicine, agriculture and pharmaceuticals

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects