데이터 전송로 확장성과 루프 선형성을 향상시킨 다중채널 수신기들에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 정덕균.Two types of serial data communication receivers that adopt a multichannel architecture for a high aggregate I/O bandwidth are presented. Two techniques for collaboration and sharing among channels are proposed to enhance the loop-linearity and channel-expandability of multichannel receivers, respectively. The first proposed receiver employs a collaborative timing scheme recovery which relies on the sharing of all outputs of phase detectors (PDs) among channels to extract common information about the timing and multilevel signaling architecture of PAM-4. The shared timing information is processed by a common global loop filter and is used to update the phase of the voltage-controlled oscillator with better rejection of per-channel noise. In addition to collaborative timing recovery, a simple linearization technique for binary PDs is proposed. The technique realizes a high-rate oversampling PD while the hardware cost is equivalent to that of a conventional 2x-oversampling clock and data recovery. The first receiver exploiting the collaborative timing recovery architecture is designed using 45-nm CMOS technology. A single data lane occupies a 0.195-mm2 area and consumes a relatively low 17.9 mW at 6 Gb/s at 1.0V. Therefore, the power efficiency is 2.98 mW/Gb/s. The simulated jitter is about 0.034 UI RMS given an input jitter value of 0.03 UI RMS, while the relatively constant loop bandwidth with the PD linearization technique is about 7.3-MHz regardless of the data-stream noise. Unlike the first receiver, the second proposed multichannel receiver was designed to reduce the hardware complexity of each lane. The receiver employs shared calibration logic among channels and yet achieves superior channel expandability with slim data lanes. A shared global calibration control, which is used in a forwarded clock receiver based on a multiphase delay-locked loop, accomplishes skew calibration, equalizer adaptation, and the phase lock of all channels during a calibration period, resulting in reduced hardware overhead and less area required by each data lane. The second forwarded clock receiver is designed in 90-nm CMOS technology. It achieves error-free eye openings of more than 0.5 UI across 9− 28 inch Nelco 4000-6 microstrips at 4− 7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm2 and consumes 56 mW at a data rate of 7 Gb/s and a supply voltage of 1.35 V.1. Introduction 1 1.1 Motivations 1.2 Thesis Organization 2. Previous Receivers for Serial-Data Communications 2.1 Classification of the Links 2.2 Clocking architecture of transceivers 2.3 Components of receiver 2.3.1 Channel loss 2.3.2 Equalizer 2.3.3 Clock and data recovery circuit 2.3.3.1. Basic architecture 2.3.3.2. Phase detector 2.3.3.2.1. Linear phase detector 2.3.3.2.2. Binary phase detector 2.3.3.3. Frequency detector 2.3.3.4. Charge pump 2.3.3.5. Voltage controlled oscillator and delay-line 2.3.4 Loop dynamics of PLL 2.3.5 Loop dynamics of DLL 3. The Proposed PLL-Based Receiver with Loop Linearization Technique 3.1 Introduction 3.2 Motivation 3.3 Overview of binary phase detection 3.4 The proposed BBPD linearization technique 3.4.1 Architecture of the proposed PLL-based receiver 3.4.2 Linearization technique of binary phase detection 3.4.3 Rotational pattern of sampling phase offset 3.5 PD gain analysis and optimization 3.6 Loop Dynamics of the 2nd-order CDR 3.7 Verification with the time-accurate behavioral simulation 3.8 Summary 4. The Proposed DLL-Based Receiver with Forwarded-Clock 4.1 Introduction 4.2 Motivation 4.3 Design consideration 4.4 Architecture of the proposed forwarded-clock receiver 4.5 Circuit description 4.5.1 Analog multi-phase DLL 4.5.2 Dual-input interpolating deley cells 4.5.3 Dedicated half-rate data samplers 4.5.4 Cherry-Hooper continuous-time linear equalizer 4.5.5 Equalizer adaptation and phase-lock scheme 4.6 Measurement results 5. Conclusion 6. BibliographyDocto

INJECTION-LOCKING TECHNIQUES FOR MULTI-CHANNEL ENERGY EFFICIENT TRANSMITTER

Ph.DDOCTOR OF PHILOSOPH

Optical MEMS

Optical microelectromechanical systems (MEMS), microoptoelectromechanical systems (MOEMS), or optical microsystems are devices or systems that interact with light through actuation or sensing at a micro- or millimeter scale. Optical MEMS have had enormous commercial success in projectors, displays, and fiberoptic communications. The best-known example is Texas Instruments’ digital micromirror devices (DMDs). The development of optical MEMS was impeded seriously by the Telecom Bubble in 2000. Fortunately, DMDs grew their market size even in that economy downturn. Meanwhile, in the last one and half decade, the optical MEMS market has been slowly but steadily recovering. During this time, the major technological change was the shift of thin-film polysilicon microstructures to single-crystal–silicon microsructures. Especially in the last few years, cloud data centers are demanding large-port optical cross connects (OXCs) and autonomous driving looks for miniature LiDAR, and virtual reality/augmented reality (VR/AR) demands tiny optical scanners. This is a new wave of opportunities for optical MEMS. Furthermore, several research institutes around the world have been developing MOEMS devices for extreme applications (very fine tailoring of light beam in terms of phase, intensity, or wavelength) and/or extreme environments (vacuum, cryogenic temperatures) for many years. Accordingly, this Special Issue seeks to showcase research papers, short communications, and review articles that focus on (1) novel design, fabrication, control, and modeling of optical MEMS devices based on all kinds of actuation/sensing mechanisms; and (2) new developments of applying optical MEMS devices of any kind in consumer electronics, optical communications, industry, biology, medicine, agriculture, physics, astronomy, space, or defense

Linac4 Technical Design Report

Linac4 is an H- linear accelerator, intended to replace Linac2 as injector to the PS Booster (PSB). By delivering to the PSB a beam at 160 MeV energy, Linac4 will provide the conditions to double the brightness and intensity of the beam from the PSB, thus removing the first bottleneck towards higher brightness for the LHC and simplifying operation. Moreover, this new linac constitutes an essential component of any of the envisaged LHC upgrade scenarios and could open the way to future extensions of the CERN accelerator complex towards higher performance. This Technical Design Report presents a detailed technical overview of the Linac4 design as it stands at end 2006

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ATS-6 engineering performance report. Volume 2: Orbit and attitude controls

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Zeroth-order design report for the next linear collider. Volume 1

This Zeroth Order Design Report (ZDR) for the Next Linear Collider (NLC) has been completed as a feasibility study for a TeV-scale linear collider that incorporates a room-temperature accelerator powered by rf microwaves at 11.424 GHz--similar to that presently used in the SLC, but at four times the rf frequency. The purpose of this study is to examine the complete systems of such a collider, to understand how the parts fit together, and to make certain that every required piece has been included. The design presented here is not fully engineered in any sense, but to be assured that the NLC can be built, attention has been given to a number of critical components and issues that present special challenges. More engineering and development of a number of mechanical and electrical systems remain to be done, but the conclusion of this study is that indeed the NLC is technically feasible and can be expected to reach the performance levels required to perform research at the TeV energy scale. Volume one covers the following: the introduction; electron source; positron source; NLC damping rings; bunch compressors and prelinac; low-frequency linacs and compressors; main linacs; design and dynamics; and RF systems for main linacs

Cumulative index to NASA Tech Briefs, 1986-1990, volumes 10-14

Tech Briefs are short announcements of new technology derived from the R&D activities of the National Aeronautics and Space Administration. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This cumulative index of Tech Briefs contains abstracts and four indexes (subject, personal author, originating center, and Tech Brief number) and covers the period 1986 to 1990. The abstract section is organized by the following subject categories: electronic components and circuits, electronic systems, physical sciences, materials, computer programs, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences