Direct sampling receivers for broadband communications

Today everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for those connected devices. It is always a dream to design a Software-Defined Radio (SDR) supporting different standards solely based on the software configuration. As integrated-circuit (IC) manufacture and design advance, a partial of SDR can be realized. This thesis investigates one of the most important parts in a SDR: the analog design of a direct sampling (DS) receiver, which mainly consists of a broadband RF front end and a wideband ADC. Especially, a DS receiver shows a great flexibility and efficiency for the simultaneous reception of multiple channels comparing with the traditional parallelism of superheterodyne structure. The research contributions of this work include (1) demonstration and comparative analysis of two new architectures of broadband RFPGAs: voltage-mode: RFPGA-V and current-mode: RFPGA-I. RFPGA-V and RFPGA-I utilize an innovative interpolation method and current steering approach, respectively, to achieve a fine gain step of 0.25-dB over 40-dB gain range for several GHz frequency range. Besides, with innovative design, no off-chip inductor is needed for the both RFPGAs. (2) The design of a 5-GS/s 10b time-interleaved SAR. The ADC power efficiency is significantly improved by many design techniques: the low-energy CDAC switching scheme, optimized input common-mode voltage for comparator, optimal reduced radix-2 capacitor ratio for low-power reference buffers and higher conversion speed, etc. The lane-to-lane mismatches in a time-interleave ADC are minimized by using optimal floor plan and then are calibrated digitally. Three prototypes: the broadband RF front ends with RFPGA-V, the broadband RF front ends with RFPGA-I and a 5-GHz ADC, are fabricated to verify the proposed ideas in 28nm CMOS technology.Electrical and Computer Engineerin

High performance continuous-time filters for information transfer systems

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications

The Design, Testing, and Analysis of a Constant Jammer for the Bluetooth Low Energy (BLE) Wireless Communication Protocol

The decreasing cost of web-enabled smart devices utilizing embedded processors, sensors, and wireless communication hardware have created an optimal ecosystem for the Internet of Things (IoT). IEEE802.15.4, IEEE802.11ah, WirelessHART, ZigBee Smart Energy, Bluetooth (BT), and Bluetooth Low Energy (BLE) are amongst the most commonly used wireless standards for IoT systems. Each of these standards has tradeoffs concerning power consumption, range of communication, network formation, security, reliability, and ease of implementation. The most widely used standards for IoT are Bluetooth, BLE, and Zigbee. This paper discusses the vulnerabilities in the implementation of the PHY and link layers of BLE. The link layer defines the scheme for establishing a link between two devices. Scanning devices are able to establish communication with other devices that are sending advertising packets. These advertising packets are sent out in a deterministic fashion. The advertising channels for BLE, specified by the PHY layer, are Channels 37, 38, and 39, at center frequencies 2.402, 2.426, and 2.480 GHz, respectively. This scheme for establishing a connection seems to introduce an unintentional gap in the security of the protocol. Creating and transmitting tones with center frequencies corresponding to those of the advertising channels, a victim BLE device will be unable to establish a connection with another BLE device. Jamming a mesh network of BLE devices relies on this same concept. The proposed jamming system is an inexpensive one which utilizes the following hardware. Three individual synthesizers, a microcontroller (MCU), Wilkinson power combiner, power amplifier, and antenna, integrated on a single PCB, are used to transmit a 3-tone signal. Due to the unprecedented nature of the COVID-19 pandemic, necessary adjustments were made to the jammer system design. In the first modified jamming scheme, a single synthesizer evaluation board, power amplifier, and antenna, are used to transmit jamming tones in the form of a frequency hop. Limitations of the frequency hop approach necessitated a second modified scheme. In this second scheme a synthesizer and two Software Defined Radios (SDR), connected to a personal computer, continuously generate three individual jamming tones. The proposed jammer and the modified ones all classify as constant jammers as the transmission of jamming signals is continuous. Both modified jamming schemes are tested. The results of jamming using the second modified scheme validate the objective of simultaneous jamming of the advertising channels of BLE devices. The success of the modified scheme enables the original goal of creating a relatively inexpensive custom PCB for BLE advertising channel jamming. By exploiting the weakness of the BLE protocol, the hope is to have the governing body for Bluetooth, Bluetooth Special Interest Group (SIG), improve security for the future releases of BLE

Adaptive multilevel quadrature amplitude radio implementation in programmable logic

Emerging broadband wireless packet data networks are increasingly employing spectrally efficient modulation methods like Quadrature Amplitude Modulation (QAM) to increase the channel efficiency and maximize data throughput. Unfortunately, the performance of high level QAM modulations in the wireless channel is sensitive to channel imperfections and throughput is degraded significantly at low signal-to-noise ratios due to bit errors and packet retransmission. To obtain a more “robust” physical layer, broadband systems are employing multilevel QAM (M-QAM) to mitigate this reduction in throughput by adapting the QAM modulation level to maintain acceptable packet error rate (PER) performance in changing channel conditions. This thesis presents an adaptive M-QAM modem hardware architecture, suitable for use as a modem core for programmable software defined radios (SDRs) and broadband wireless applications. The modem operates in “burst” mode, and can reliably synchronize to different QAM constellations “burst-by-burst”. Two main improvements exploit commonality in the M-QAM constellations to minimize the redundant hardware required. First, the burst synchronization functions (carrier, clock, amplitude, and modulation level) operate reliably without prior knowledge of the QAM modulation level used in the burst. Second, a unique bit stuffing and shifting technique is employed which supports variable bit rate operation, while reducing the core signal processing functions to common hardware for all constellations. These features make this architecture especially attractive for implementation with Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs); both of which are becoming popular for highly integrated, cost-effective wireless transceivers

Diseño de un estudio de postproducción de audio para cine acorde al formato Dolby Digital 5.1

El proyecto intenta ofrecer un acercamiento al diseño de estudios de postproducción de audio para cine. Para ello, comienza introduciendo la historia del audio en el cine y el desarrollo de los sistemas de audio multicanal para continuar estudiando todos los aspectos relativos al diseño de este tipo de estudios, incluyendo las particularidades aplicables en producciones de audio multicanal. Finalmente, los conceptos estudiados son aplicados en una simulación acústica.This project tries to be an approach to audio mixing rooms design for cinema applications. In order to do that, it begins with a little history about audio in cinema and the development of multichannel audio systems to continue studying all the topics regarding the field of mixing rooms design, including the particularities of multichannel audio productions. Finally, all these topics are applied on an acoustic simulation.Universidad de Sevilla. Ingeniería Telecomunicació

High capacity photonic integrated switching circuits

As the demand for high-capacity data transfer keeps increasing in high performance computing and in a broader range of system area networking environments; reconfiguring the strained networks at ever faster speeds with larger volumes of traffic has become a huge challenge. Formidable bottlenecks appear at the physical layer of these switched interconnects due to its energy consumption and footprint. The energy consumption of the highly sophisticated but increasingly unwieldy electronic switching systems is growing rapidly with line rate, and their designs are already being constrained by heat and power management issues. The routing of multi-Terabit/second data using optical techniques has been targeted by leading international industrial and academic research labs. So far the work has relied largely on discrete components which are bulky and incurconsiderable networking complexity. The integration of the most promising architectures is required in a way which fully leverages the advantages of photonic technologies. Photonic integration technologies offer the promise of low power consumption and reduced footprint. In particular, photonic integrated semiconductor optical amplifier (SOA) gate-based circuits have received much attention as a potential solution. SOA gates exhibit multi-terahertz bandwidths and can be switched from a high-gain state to a high-loss state within a nanosecond using low-voltage electronics. In addition, in contrast to the electronic switching systems, their energy consumption does not rise with line rate. This dissertation will discuss, through the use of different kind of materials and integration technologies, that photonic integrated SOA-based optoelectronic switches can be scalable in either connectivity or data capacity and are poised to become a key technology for very high-speed applications. In Chapter 2, the optical switching background with the drawbacks of optical switches using electronic cores is discussed. The current optical technologies for switching are reviewed with special attention given to the SOA-based switches. Chapter 3 discusses the first demonstrations using quantum dot (QD) material to develop scalable and compact switching matrices operating in the 1.55µm telecommunication window. In Chapter 4, the capacity limitations of scalable quantum well (QW) SOA-based multistage switches is assessed through experimental studies for the first time. In Chapter 5 theoretical analysis on the dependence of data integrity as ultrahigh line-rate and number of monolithically integrated SOA-stages increases is discussed. Chapter 6 presents some designs for the next generation of large scale photonic integrated interconnects. A 16x16 switch architecture is described from its blocking properties to the new miniaturized elements proposed. Finally, Chapter 7 presents several recommendations for future work, along with some concluding remark

Analog baseband circuits for WCDMA direct-conversion receivers

This thesis describes the design and implementation of analog baseband circuits for low-power single-chip WCDMA direct-conversion receivers. The reference radio system throughout the thesis is UTRA/FDD. The analog baseband circuit consists of two similar channels, which contain analog channel-select filters, programmable-gain amplifiers, and circuits that remove DC offsets. The direct-conversion architecture is described and the UTRA/FDD system characteristics are summarized. The UTRA/FDD specifications define the performance requirement for the whole receiver. Therefore, the specifications for the analog baseband circuit are obtained from the receiver requirements through calculations performed by hand. When the power dissipation of an UTRA/FDD direct-conversion receiver is minimized, the design parameters of an all-pole analog channel-select filter and the following Nyquist rate analog-to-digital converter must be considered simultaneously. In this thesis, it is shown that minimum power consumption is achieved with a fifth-order lowpass filter and a 15.36-MS/s Nyquist rate converter that has a 7- or 8-bit resolution. A fifth-order Chebyshev prototype with a passband ripple of 0.01 dB and a −3-dB frequency of 1.92-MHz is adopted in this thesis. The error-vector-magnitude can be significantly reduced by using a first-order 1.4-MHz allpass filter. The selected filter prototype fulfills all selectivity requirements in the analog domain. In this thesis, all the filter implementations use the opamp-RC technique to achieve insensitivity to parasitic capacitances and a high dynamic range. The adopted technique is analyzed in detail. The effect of the finite opamp unity-gain bandwidth on the filter frequency response can be compensated for by using passive methods. Compensation schemes that also track the process and temperature variations have been developed. The opamp-RC technique enables the implementation of low-voltage filters. The design and simulation results of a 1.5-V 2-MHz lowpass filter are discussed. The developed biasing scheme does not use any additional current to achieve the low-voltage operation, unlike the filter topology published previously elsewhere. Methods for removing DC offsets in UTRA/FDD direct-conversion receivers are presented. The minimum areas for cascaded AC couplings and DC-feedback loops are calculated. The distortion of the frequency response of a lowpass filter caused by a DC-feedback loop connected over the filter is calculated and a method for compensating for the distortion is developed. The time constant of an AC coupling can be increased using time-constant multipliers. This enables the implementation of AC couplings with a small silicon area. Novel time-constant multipliers suitable for systems that have a continuous reception, such as UTRA/FDD, are presented. The proposed time-constant multipliers only require one additional amplifier. In an UTRA/FDD direct-conversion receiver, the reception is continuous. In a low-power receiver, the programmable baseband gain must be changed during reception. This may produce large, slowly decaying transients that degrade the receiver performance. The thesis shows that AC-coupling networks and DC-feedback loops can be used to implement programmable-gain amplifiers, which do not produce significant transients when the gain is altered. The principles of operation, the design, and the practical implementation issues of these amplifiers are discussed. New PGA topologies suitable for continuously receiving systems have been developed. The behavior of these circuits in the presence of strong out-of-channel signals is analyzed. The interface between the downconversion mixers and the analog baseband circuit is discussed. The effect of the interface on the receiver noise figure and the trimming of mixer IIP2 are analyzed. The design and implementation of analog baseband circuits and channel-select filters for UTRA/FDD direct-conversion receivers are discussed in five application cases. The first case presents the analog baseband circuit for a chip-set receiver. A channel-select filter that has an improved dynamic range with a smaller supply current is presented next. The third and fifth application cases describe embedded analog baseband circuits for single-chip receivers. In the fifth case, the dual-mode analog baseband circuit of a quad-mode receiver designed for GSM900, DCS1800, PCS1900, and UTRA/FDD cellular systems is described. A new, highly linear low-power transconductor is presented in the fourth application case. The fourth application case also describes a channel-select filter. The filter achieves +99-dBV out-of-channel IIP2, +45-dBV out-of-channel IIP3 and 23-μVRMS input-referred noise with 2.6-mA current from a 2.7-V supply. In the fifth application case, a corresponding performance is achieved in UTRA/FDD mode. The out-of-channel IIP2 values of approximately +100 dBV achieved in this work are the best reported so far. This is also the case with the figure of merits for the analog channel-select filter and analog baseband circuit described in the fourth and fifth application cases, respectively. For equal power dissipation, bandwidth, and filter order, these circuits achieve approximately 10 dB and 15 dB higher spurious-free dynamic ranges, respectively, when compared to implementations that are published elsewhere and have the second best figure of merits.reviewe

Remote powered system for passive optical networks

Mestrado em Engenharia Electrónica e TelecomunicaçõesAs redes passivas são cada vez mais uma realidade. Os standards estão a desenvolver-se rapidamente (NG-PON, G-PON, etc), e cada vez mais o consumidor final tem maior necessidade de largura de banda, que, numa primeira fase, irá certamente, ser distribuída por redes passivas integralmente ópticas. As redes passivas são, por si, uma solução interessante para os operadores, pois, sendo passivas minimizam os custos de manutenção. No entanto, o reverso desta passividade e transparência, é que estas podem ser alteradas por simples aumento do número de ramais de uma forma independente e potencialmente incontrolada. Um aumento do tráfego, bem como um crescente de procura de novos serviços e larguras de banda, vêm forçar o desenvolvimento de novas tecnologias que permitam um redimensionamento e redefinição da rede, nomeadamente nós ópticos transparentes. O objectivo principal deste trabalho é estudar os processos de alimentação remota de sistemas de comutação e reconfiguração para utilização em redes ópticas passivas, e fazer uma implementação de alguns modelos para teste. De salientar que este projecto enquadra-se no projecto Europeu “SARDANA” e nas redes de excelência “BONE” e “Euro-FOS”. ABSTRACT: The passive networks are becoming a reality. The Standards are evolving rapidly (NG-PON, G-PON, etc), and now, the consumer, more than ever, has a major necessity for bandwidth, which, in a first stage, will certainly be distributed by fully passive optical networks. The passive networks are, on their own, an interesting solution for operators, because, being passive, minimize the maintenance costs. However, the other side of the passiveness and transparency is that it can be altered by simple increase of the number of branches in a independent way and potentially uncontrolled. An increase of traffic, as an increasing search of new services and bandwidth, are forcing the development of new technologies which will allow a network resizing and redefinition, in particular, the transparent optical nodes. The main objective of this work is study the remote powering processes for commutable and reconfigurable systems, to be used in passive optical networks, and implementing some models for testing. Note that this Project falls within the European project “SARDANA” and in the networks of excellence “BONE” and “Euro-FOS”

Co-channel Blocker and Self-Interferer Tolerant Receiver Architectures for MIMO and Full-Duplex MIMO Receivers

This research focuses on receiver architectures which enable better spectral e�ciency by handling blockers in the same spectral range as the signal. The presence of such blockers, without the use of blocker cancelling/�ltering techniques leads to gain compression and hence, consequent performance degradation of receivers leading to reduced spectrum e�ciency. Two approaches have been devised, implemented in silicon and measured to demonstrate that they alleviate the problems associated with blockers. A system capable of handling co-channel spatially separated blockers is implemented in the �rst work and another system capable of handling self-interference caused due to the transmitter during full-duplex operation constitutes the second work. In the �rst work, a 4-channel phased array based on a novel architecture incorporating a coupler and a noise-cancelling LNA in combination with a polyphase �lter was implemented to eliminate spatial co-channel blockers. This approach allows signal reception from all directions except from the direction of the blocker providing better than 20dB blocker cancellation in the X-band. The second work is aimed at achieving true simultaneous transmit-and-receive (STAR) performance through a hybrid coupler based full-duplex integrated N-path based circulator-Rx architecture. STAR radios enable higher spectrum e�ciency and dynamic spectrum access. Integrating the shared antenna-interface is attractive for small-form factor and MIMO channel estimation. Implemented for frequencies ranging from 550MHz to 900MHz this work addresses the challenge of low-noise wideband self-interference-cancellation by demonstrating a wide band hybrid-coupler circulator antenna interface using N-path mixers that achieves low noise �gure while preserving the linearity of passive-mixer �rst receiver. Better than +5.5dBm power handling of self-interference while providing over 40dB average cancellation over a bandwidth of 56MHz with a 2.7dB noise �gure has been measured. Further, the full-duplex circulator architecture has been expanded to a MIMO implementation wherein we demonstrate a 65nm CMOS 2.2GHz 2x2 FD MIMO RX that achieves up to 35/45dB average self-interference-cancellation (SIC) across 40/20MHz BW with more than 42dB/53dB average cross-talk (CT)-SIC across 40/20MHz BW. Interference cancellation mechanisms cause < 2.1dB degradation in RX NF and allows an overall TX power handling of +14dBm enabled by clock bootstrapping