Design of a low-voltage op-amp-less ASDM to linearise VCO-ADC

A very simple asynchronous sigma delta modulator design for linearisation of VCO ADC's is presented. The circuit only consists of a passive feedback filter and a Schmitt Trigger. By proper sizing, the non-linearity error can be reduced to well below 0.12% for input signals that go almost rail-to-rail. The design has been manufactured in the low power version of TSMC 65 nm technology and was measured at a 1 V power supply

Expression of renal distal tubule transporters TRPM6 and NCC in a rat model of cyclosporine nephrotoxicity and effect of EGF treatment

Renal magnesium (Mg(2+)) and sodium (Na(+)) loss are well-known side effects of cyclosporine (CsA) treatment in humans, but the underlying mechanisms still remain unclear. Recently, it was shown that epidermal growth factor (EGF) stimulates Mg(2+) reabsorption in the distal convoluted tubule (DCT) via TRPM6 (Thebault S, Alexander RT, Tiel Groenestege WM, Hoenderop JG, Bindels RJ. J Am Soc Nephrol 20: 78-85, 2009). In the DCT, the final adjustment of renal sodium excretion is regulated by the thiazide-sensitive Na(+)-Cl(-) cotransporter (NCC), which is activated by the renin-angiotensin-aldosterone system (RAAS). The aim of this study was to gain more insight into the molecular mechanisms of CsA-induced hypomagnesemia and hyponatremia. Therefore, the renal expression of TRPM6, TRPM7, EGF, EGF receptor, claudin-16, claudin-19, and the NCC, and the effect of the RAAS on NCC expression, were analyzed in vivo in a rat model of CsA nephrotoxicity. Also, the effect of EGF administration on these parameters was studied. CsA significantly decreased the renal expression of TRPM6, TRPM7, NCC, and EGF, but not that of claudin-16 and claudin-19. Serum aldosterone was significantly lower in CsA-treated rats. In control rats treated with EGF, an increased renal expression of TRPM6 together with a decreased fractional excretion of Mg(2+) (FE Mg(2+)) was demonstrated. EGF did not show this beneficial effect on TRPM6 and FE Mg(2+) in CsA-treated rats. These data suggest that CsA treatment affects Mg(2+) homeostasis via the downregulation of TRPM6 in the DCT. Furthermore, CsA downregulates the NCC in the DCT, associated with an inactivation of the RAAS, resulting in renal sodium loss

Uma arquitetura de modulação sigma-delta assíncrona em ultra-baixa potência para aplicações biomédicas.

Esse trabalho apresenta o projeto e a fabricação de um circuito integrado modulador Σ-Δ assíncrono especialmente projetado para aplicações biomédicas. Desenvolvido em processo Digital IBM 130-nm, utiliza técnicas de polarização em inversão fraca e leiaute distribuído de transistores halo-implantados, opera com alimentação de 0,25-V e consome 15-nW de potência. O projeto foi guiado pela teoria clássica que modela o modulador Σ-Δ assíncrono segundo uma malha realimentada constituída de um elemento linear e de um elemento não-linear. Um circuito amplificador operacional de transcondutância é utilizado em conjunto com um arranjo capacitivo para construir um integrador -C, elemento linear. O elemento não-linear é realizado por um circuito oscilador de relaxação que opera comutando um arranjo capacitivo através de uma cadeia de inversores CMOS e não envolve polarização adicional, reduzindo o consumo energético. Foram desenvolvidos dois modelos que descrevem a sua operação e fornecem as condições necessárias para que o circuito opere como um modulador Σ-Δ assíncrono além de análises de descasamento que mostram que o circuito é passível de calibração, quando necessário. A caracterização do protótipo comprova as características de frequência e histerese de tensão descritas na modelagem e mostra que alimentado com 0,25-V, consome 15-nW, alcançando 9 bits de resolução em uma banda de 30-Hz, que se traduzem em aproximadamente 300-V de resolução de tensão para o sinal de 150-m aplicado. Esses resultados são condizentes com aplicações biomédicas portáteis ou mesmo implantáveis, uma vez que requerem baixo consumo energético e resolução moderada trabalhando em bandas reduzidas de frequência

A 12-bit SAR ADC for a flexible tactile sensor

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) are some of the most efficient ADC topologies available, allowing excellent performance values at low power consumption across a wide range of sampling frequencies. The proposed ADC is aimed at a tactile sensor application, requiring a low-noise and lowpower solution. In addition, it should have high SNDR to detect even the weakest signals with precision. This thesis presents a 12-bit 400 kS/s SAR ADC implemented in a 180 nm CMOS technology for such a task. The designed SAR ADC uses a hybrid R-C DAC topology consisting of a chargescaling MSB DAC and a voltage-scaling LSB DAC, allowing a good trade-off between power consumption, layout area and performance while keeping the total DAC capacitance under reasonable values. Bootstrapped switches have been implemented to preserve high-linearity during the sampling period. A double-tail dynamic comparator has been designed to obtain a low-noise measurement while ensuring suitable delay values. Finally, regarding the logic, an asynchronous implementation and the conventional switching algorithm provide a simple but effective solution to supply the digital signals of the design. Pre-layout noise simulations with input frequencies around 200 kHz show SNDR values of 72.07 dB, corresponding to an ENOB of 11.67 bits. The total power consumption is 365 ?W while the Walden and Schreier figure-of-merit (FoM) correspond to values of 275 fJ/conversion and 160 dB, respectively

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Resource-Constrained Acquisition Circuits for Next Generation Neural Interfaces

The development of neural interfaces allowing the acquisition of signals from the cortex of the brain has seen an increasing amount of interest both in academic research as well as in the commercial space due to their ability to aid people with various medical conditions, such as spinal cord injuries, as well as their potential to allow more seamless interactions between people and machines. While it has already been demonstrated that neural implants can allow tetraplegic patients to control robotic arms, thus to an extent returning some motoric function, the current state of the art often involves the use of heavy table-top instruments connected by wires passing through the patient’s skull, thus making the applications impractical and chronically infeasible. Those limitations are leading to the development of the next generation of neural interfaces that will overcome those issues by being minimal in size and completely wireless, thus paving a way to the possibility of their chronic application. Their development however faces several challenges in numerous aspects of engineering due to constraints presented by their minimal size, amount of power available as well as the materials that can be utilised. The aim of this work is to explore some of those challenges and investigate novel circuit techniques that would allow the implementation of acquisition analogue front-ends under the presented constraints. This is facilitated by first giving an overview of the problematic of recording electrodes and their electrical characterisation in terms of their impedance profile and added noise that can be used to guide the design of analogue front-ends. Continuous time (CT) acquisition is then investigated as a promising signal digitisation technique alternative to more conventional methods in terms of its suitability. This is complemented by a description of practical implementations of a CT analogue-to-digital converter (ADC) including a novel technique of clockless stochastic chopping aimed at the suppression of flicker noise that commonly affects the acquisition of low-frequency signals. A compact design is presented, implementing a 450 nW, 5.5 bit ENOB CT ADC, occupying an area of 0.0288 mm2 in a 0.18 μm CMOS technology, making this the smallest presented design in literature to the best of our knowledge. As completely wireless neural implants rely on power delivered through wireless links, their supply voltage is often subject to large high frequency variations as well voltage uncertainty making it necessary to design reference circuits and voltage regulators providing stable reference voltage and supply in the constrained space afforded to them. This results in numerous challenges that are explored and a design of a practical implementation of a reference circuit and voltage regulator is presented. Two designs in a 0.35 μm CMOS technology are presented, showing respectively a measured PSRR of ≈60 dB and ≈53 dB at DC and a worst-case PSRR of ≈42 dB and ≈33 dB with a less than 1% standard deviation in the output reference voltage of 1.2 V while consuming a power of ≈7 μW. Finally, ΣΔ modulators are investigated for their suitability in neural signal acquisition chains, their properties explained and a practical implementation of a ΣΔ DC-coupled neural acquisition circuit presented. This implements a 10-kHz, 40 dB SNDR ΣΔ analogue front-end implemented in a 0.18 μm CMOS technology occupying a compact area of 0.044 μm2 per channel while consuming 31.1 μW per channel.Open Acces

Energy-Efficient Time-Based Encoders and Digital Signal Processors in Continuous Time

Continuous-time (CT) data conversion and continuous-time digital signal processing (DSP) are an interesting alternative to conventional methods of signal conversion and processing. This alternative proposes time-based encoding that may not suffer from aliasing; shows superior spectral properties (e.g. no quantization noise floor); and enables time-based, event-driven, flexible signal processing using digital circuits, thus scaling well with technology. Despite these interesting features, this approach has so far been limited by the CT encoder, due to both its relatively poor energy efficiency and the constraints it imposes on the subsequent CT DSP. In this thesis, we present three principles that address these limitations and help improve the CT ADC/DSP system. First, an adaptive-resolution encoding scheme that achieves first-order reconstruction with simple circuitry is proposed. It is shown that for certain signals, the scheme can significantly reduce the number of samples generated per unit of time for a given accuracy compared to schemes based on zero-order-hold reconstruction, thus promising to lead to low dynamic power dissipation at the system level. Presented next is a novel time-based CT ADC architecture, and associated encoding scheme, that allows a compact, energy-efficient circuit implementation, and achieves first-order quantization error spectral shaping. The design of a test chip, implemented in a 0.65-V 28-nm FDSOI process, that includes this CT ADC and a 10-tap programmable FIR CT DSP to process its output is described. The system achieves 32 dB – 42 dB SNDR over a 10 MHz – 50 MHz bandwidth, occupies 0.093 mm2, and dissipates 15 µW–163 µW as the input amplitude goes from zero to full scale. Finally, an investigation into the possibility of CT encoding using voltage-controlled oscillators is undertaken, and it leads to a CT ADC/DSP system architecture composed primarily of asynchronous digital delays. The latter makes the system highly digital and technology-scaling-friendly and, hence, is particularly attractive from the point of view of technology migration. The design of a test chip, where this delay-based CT ADC/DSP system architecture is used to implement a 16-tap programmable FIR filter, in a 1.2-V 28-nm FDSOI process, is described. Simulations show that the system will achieve a 33 dB – 40 dB SNDR over a 600 MHz bandwidth, while dissipating 4 mW