Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception

Blocker Tolerant Radio Architectures

Future radio platforms have to be inexpensive and deal with a variety of co- existence issues. The technology trend during the last few years is towards system- on-chip (SoC) that is able to process multiple standards re-using most of the digital resources. A major bottle-neck to this approach is the co-existence of these standards operating at different frequency bands that are hitting the receiver front-end. So the current research is focused on the power, area and performance optimization of various circuit building blocks of a radio for current and incoming standards. Firstly, a linearization technique for low noise amplifiers (LNAs) called, Robust Derivative Superposition (RDS) method is proposed. RDS technique is insensitive to Process Voltage and Temperature (P.V.T.) variations and is validated with two low noise transconductance amplifier (LNTA) designs in 0.18µm CMOS technology. Measurement results from 5 dies of a resistive terminated LNTA shows that the pro- posed method improves IM3 over 20dB for input power up to -18dBm, and improves IIP_(3) by 10dB. A 2V inductor-less broadband 0.3 to 2.8GHz balun-LNTA employing the proposed RDS linearization technique was designed and measured. It achieves noise figure of 6.5dB, IIP3 of 16.8dBm, and P1dB of 0.5dBm having a power consumption of 14.2mW. The balun LNTA occupies an active area of 0.06mm2. Secondly, the design of two high linearity, inductor-less, broadband LNTAs employing noise and distortion cancellation techniques is presented. Main design issues and the performance trade-offs of the circuits are discussed. In the fully differential architecture, the first LNTA covers 0.1-2GHz bandwidth and achieves a minimum noise figure (NFmin) of 3dB, IIP_(3) of 10dBm and a P_(1dB) of 0dBm while dissipating 30.2mW. The 2^(nd) low power bulk driven LNTA with 16mW power consumption achieves NFmin of 3.4dB, IIP3 of 11dBm and 0.1-3GHz bandwidth. Each LNTA occupy an active area of 0.06mm2 in 45nm CMOS. Thirdly, a continuous-time low-pass ∆ΣADC equipped with design techniques to provide robustness against loop saturation due to blockers is presented. Loop over- load detection and correction is employed to improve the ADC’s tolerance to blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADC’s blocker tolerance, a minimally-invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. An ADC prototype is implemented in a 90nm CMOS technology and experimentally it achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500MHz and 17.1mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5dBFS while the conventional feed-forward modulator becomes unstable at -23.5dBFS of blocker power. The proposed blocker rejection techniques are minimally-invasive and take less than 0.3µsec to settle after a strong agile blocker appears. Finally, a new radio partitioning methodology that gives robust analog and mixed signal radio development in scaled technology for SoC integration, and the co-design of RF FEM-antenna system is presented. Based on the proposed methodology, a CMOS RF front-end module (FEM) with power amplifier (PA), LNA and transmit/receive switch, co-designed with antenna is implemented. The RF FEM circuit is implemented in a 32nm CMOS technology. Post extracted simulations show a noise figure < 2.5dB, S_(21) of 14dB, IIP3 of 7dBm and P1dB of -8dBm for the receiver. Total power consumption of the receiver is 11.8mW from a 1V supply. On the trans- mitter side, PA achieves peak RF output power of 22.34dBm with peak power added efficiency (PAE) of 65% and PAE of 33% with linearization at -6dB power back off. Simulations show an efficiency of 80% for the miniaturized dipole antenna

Analysis And Design Of Wideband Passive Mixer-First Receivers

This dissertation focuses on the design of wideband SAW-less receivers for softwaredefined radios. The entire body of work is based on a single RF front-end architecture type: a passive mixer connected directly to the antenna port of the radio, without an LNA or matching network up front. This structure is inherently wideband which allows for a single receiver front-end to operate at a wide range of frequencies, as tuned by its local oscillator (LO). Additionally, the mixer exhibits the property of transparency from the baseband port of the radio to the RF port of the radio, and vice versa. The focus of the first half of the thesis is on developing a simple theoretical framework for the impedance characteristics of the passive mixer, and implementing a maximally flexible receiver which utilizes the mixer's transparency to the fullest extent. Additionally, it is shown that mixing with 8 non-overlapping phases instead of the traditional 4 has benefits beyond harmonic rejection extending to improved noise performance and increased impedance tuning range. This receiver exhibits low noise figure (~3dB), excellent wideband linearity (IIP3[GREATER-THAN OR EQUAL TO]25dBm), and unprecedented RF impedance control from the baseband side of the passive mixer. Another wideband receiver is presented which explores increasing the number of LO phases even further to 16 and 32, increasing the impedance matching range. The same chip contains a circuit technique for alleviating the shunting effects of LO phase overlap on mixer conversion gain, noise, and impedance match range. Finally in a new design, the power consumption of the receiver architecture is decreased by a factor of 5x (and not scaling with RF frequency). This is done using a resonant LO drive with 8 non-overlapping phases, incorporating the large mixer gate capacitance directly into the LC tank of the VCO. Baseband power consumption is also reduced by reusing current in the four baseband amplifier channels, and performing harmonic rejection, all in one stage of amplification

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Systemanalyse und Entwicklung Six-Port basierter Funkempfängerarchitekturen unter Berücksichtigung analoger Störeffekte

Due to the increasing demand of broadband capability and reconfigurability for mobile applications, there is an enormous interest to develop appropriate analog receiver front-ends. In this respect, one promising candidate group is the Six-Port-based direct conversion receiver. The presented work focuses on the investigation of Six-Port-based mobile receiver front-ends with their specific systematical signal processing. Thereby, issues of spurious interfering signals which are generated within the down conversion process of such receivers are of special interest. Based on a comprehensive description of the analog signal processing within additive frequency conversion, a reason could be identified why existing Six-Port receivers have not found any practical application in mobile communication yet – the dynamic DC-offset. With this insight compensation techniques were developed to overcome the negative influences of the dynamic DC-offset. Furthermore, this work presents novel Six-Port-based receiver architectures which, on the one hand, keep the advantages of additive mixing systems like: low power consumption, broadband capability and simplicity of implementation especially for mm-wave transmissions. On the other hand, these novel architectures comprise compensation techniques such that systematically generated spurious signals are inherently compensated in the analog part of the receiver. Moreover, the influence of impairments of phase and amplitude within the IQ-branches of a receiver was investigated. The resulting, unwanted IQ-imbalance was shown to be a mixing method (multiplicative or additive) independent spurious effect. It is suggested to compensate for IQ-imbalance in the digital part of the receiver system. This can be realized with the use of adaptive algorithms. The comparison with conventional analog receiver architectures (especially homodyne receivers) with respect to the reception of today’s and future digitally modulated transmission signals indicate the proposed Six-Port-based receiver architectures to be suitable candidates to fulfill the difficult tasks of modern mobile communication