A 0.0016 mm(2) 0.64 nJ leakage-based CMOS temperature sensor

This paper presents a CMOS temperature sensor based on the thermal dependencies of the leakage currents targeting the 65 nm node. To compensate for the effect of process fluctuations, the proposed sensor realizes the ratio of two measures of the time it takes a capacitor to discharge through a transistor in the subthreshold regime. Furthermore, a novel charging mechanism for the capacitor is proposed to further increase the robustness against fabrication variability. The sensor, including digitization and interfacing, occupies 0.0016 mm2 and has an energy consumption of 47.7–633 pJ per sample. The resolution of the sensor is 0.28 °C, and the 3σ inaccuracy over the range 40–110 °C is 1.17 °C

A CMOS Smart Temperature and Humidity Sensor with Combined Readout.

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA

Reconfigurable writing architecture for reliable RRAM operation in wide temperature ranges

Resistive switching memories [resistive RAM (RRAM)] are an attractive alternative to nonvolatile storage and nonconventional computing systems, but their behavior strongly depends on the cell features, driver circuit, and working conditions. In particular, the circuit temperature and writing voltage schemes become critical issues, determining resistive switching memories performance. These dependencies usually force a design time tradeoff among reliability, device endurance, and power consumption, thereby imposing nonflexible functioning schemes and limiting the system performance. In this paper, we present a writing architecture that ensures the correct operation no matter the working temperature and allows the dynamic load of application-oriented writing profiles. Thus, taking advantage of more efficient configurations, the system can be dynamically adapted to overcome RRAM intrinsic challenges. Several profiles are analyzed regarding power consumption, temperature-variations protection, and operation speed, showing speedups near 700x compared with other published drivers

Sensors and Technologies in Spain: State-of-the-Art

The aim of this special issue was to provide a comprehensive view on the state-of-the-art sensor technology in Spain. Different problems cause the appearance and development of new sensor technologies and vice versa, the emergence of new sensors facilitates the solution of existing real problems. [...

The International Large Detector: Letter of Intent

163 pages, 91 figuresThe International Large Detector (ILD) is a concept for a detector at the International Linear Collider, ILC. The ILC will collide electrons and positrons at energies of initially 500 GeV, upgradeable to 1 TeV. The ILC has an ambitious physics program, which will extend and complement that of the Large Hadron Collider (LHC). A hallmark of physics at the ILC is precision. The clean initial state and the comparatively benign environment of a lepton collider are ideally suited to high precision measurements. To take full advantage of the physics potential of ILC places great demands on the detector performance. The design of ILD is driven by these requirements. Excellent calorimetry and tracking are combined to obtain the best possible overall event reconstruction, including the capability to reconstruct individual particles within jets for particle ow calorimetry. This requires excellent spatial resolution for all detector systems. A highly granular calorimeter system is combined with a central tracker which stresses redundancy and efficiency. In addition, efficient reconstruction of secondary vertices and excellent momentum resolution for charged particles are essential for an ILC detector. The interaction region of the ILC is designed to host two detectors, which can be moved into the beam position with a push-pull scheme. The mechanical design of ILD and the overall integration of subdetectors takes these operational conditions into account

High Resolution Active Pixel Sensor X-Ray Detectors for Digital Breast Tomosynthesis

Current large area x-ray detectors for digital breast tomosynthesis (DBT) are based on the amorphous silicon (a-Si:H) passive pixel sensor (PPS) technology. However, PPS detectors suffer from a limited resolution and high electronic noise. In this dissertation, we propose high resolution large area active pixel sensor (APS) x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) and amorphous In-Sn-Zn-O (a-ITZO) thin-film transistor (TFT) technologies to improve the imager resolution and noise properties. We evaluated the two-dimensional (2D) x-ray imaging performance as measured by the modulation transfer function (MTF), noise power spectrum (NPS) and detective quantum efficiency (DQE) for both 75 µm (Dexela 2923 MAM) and 50 µm pixel pitch (DynAMITe) CMOS APS x-ray detectors. Excellent imaging performance (DQE in the range of 0.7 – 0.3) has been achieved over the entire spatial frequency range (0 – 6.7 mm-1) at low air kerma below 10 µGy using the 75 µm pixel pitch Dexela 2923 MAM detector. The 50 μm pixel pitch DyAMITe detector has further extended the spatial resolution of the detector to 10 mm-1 with a low electronic noise of 150 e-. Also, a 2D cascaded system analysis model has been developed to describe the signal and noise transfer for the CMOS APS x-ray imaging systems. We also implemented three-dimensional (3D) cascaded system analysis to simulated the 3D MTF, NPS and DQE characteristics using DBT radiation conditions and acquisition geometries. The 3D cascaded system analysis for the DynAMITe detector was integrated with an object task function, a medical imaging display model, and the human eye contrast sensitivity function to calculate the detectability index and area under the ROC curve (AUC). It has been demonstrated that the display pixel pitch and zoom factor should be optimized to improve the AUC for detecting high contrast objects such as microcalcifications. Also, detector electronic noise of smaller than 300 e- and a high display maximum luminance (>1000 cd/cm2) are desirable to distinguish microcalcifications of 150 µm or smaller in size. For low contrast object detection, a medical imaging display with a minimum of 12 bits gray levels is needed to realize accurate luminance levels. A wide projection angle range (≥ ±30°) combined with the image gray level magnification could improve the detectability for low contrast objects especially when the anatomical background noise is high. CMOS APS x-ray detectors demonstrate both a high pixel resolution and low electronic noise, but are challenging to be fabricated in a large detector size greater than the wafer scale. Alternatively, current-mode APS (C-APS) based on a-ITZO TFTs was proposed for DBT due to the high gain, low noise, and capability to realize a large detector area. Specifically, we fabricated a-ITZO TFTs and achieved a high field-effect mobility of >30 cm2/Vs. We have also evaluated the electrical performance of a 50 µm pixel pitch a-ITZO TFT C-APS combined with an a-Si:H p+-i-n+ photodiode using SPICE simulation. The proposed C-APS circuit demonstrates a high charge gain of 885 with data line loadings considered. A pixel circuit layout and fabrication process have also been suggested. Finally, noise analysis has been applied to the a-ITZO TFT C-APS. A low electronic noise of around 239 e- has been established. The research presented in this thesis indicates that APS x-ray detectors based on both CMOS and a-ITZO TFT technologies are promising for next generation DBT systems.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/136983/1/zhaocm_1.pd

The International Linear Collider Technical Design Report - Volume 4: Detectors

The International Linear Collider Technical Design Report (TDR) describes in four volumes the physics case and the design of a 500 GeV centre-of-mass energy linear electron-positron collider based on superconducting radio-frequency technology using Niobium cavities as the accelerating structures. The accelerator can be extended to 1 TeV and also run as a Higgs factory at around 250 GeV and on the Z0 pole. A comprehensive value estimate of the accelerator is give, together with associated uncertainties. It is shown that no significant technical issues remain to be solved. Once a site is selected and the necessary site-dependent engineering is carried out, construction can begin immediately. The TDR also gives baseline documentation for two high-performance detectors that can share the ILC luminosity by being moved into and out of the beam line in a "push-pull" configuration. These detectors, ILD and SiD, are described in detail. They form the basis for a world-class experimental programme that promises to increase significantly our understanding of the fundamental processes that govern the evolution of the Universe.Comment: See also http://www.linearcollider.org/ILC/TDR . The full list of signatories is inside the Repor

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

The effects of ionising radiation on implantable MOS electronic devices

Space exploration and the rapid growth of the satellite communications industry has promoted substantial research into the effects of ionising radiation on modem electronic technology. The enabling electronics and computer processing has seen a commensurate growth in the use of radiation for diagnostic and therapeutic purposes in medicine. Numerous studies exist in both these fields but an analysis combining the fields of study to ascertain the effects of radiation on medically implantable electronics is lacking. A review of significant ground level radiation sources is presented with particular emphasis on the medical environment. Mechanisms of permanent and transient ionising radiation damage to Metal Oxide Semiconductors are summarised. Three significant sources of radiation are classified as having the ability to damage or alter the behavior of implantable electronics; Secondary neutron cosmic radiation, alpha particle radiation from the device packaging and therapeutic doses of high energy radiation. With respect to cosmic radiation, the most sensitive circuit structure within a typical microcomputer architecture is the Random Access Memory(RAM). A theoretical model which predicts the susceptibility of a RAM cell to single event upsets from secondary cosmic ray neutrons is presented. A previously unreported method for calculating the collection efficiency term in the upset model has been derived along with an extension of the model to enable estimation of multiple bit upset rates. An Implantable Cardioverter Defibrillator is used as a case example to demonstrate model applicability and test against clinical experience. The model correlates well with clinical experience and is consistent with the expected geographical variations of the secondary cosmic ray neutron flux. This is the first clinical data set obtained indicating the effects of cosmic radiation on implantable devices. Importantly, it may be used to predict the susceptibility of future implantable device designs to cosmic radiation. The model is also used as a basis for developing radiation hardened circuit techniques and system design. A review of methods to radiation harden electronics to single event upsets is used to recommend methods applicable to the low power/small area constraints of implantable systems