A low-power delta-sigma modulator ADC for sensor system applications

This paper discusses a third-order tri-level quantizer delta-sigma modulator analog-digital converter (ADC) for cascaded integrators with distributed feedback (CIFB) and cascaded integrators with distributed feedforward (CIFF) structure for sensor system applications. The signal transfer function (STF) and noise transfer function (NTF) discussed for poles and zeroes. Oversampling ratio (OSR) and different quantizer level presented for the modulator structure to trade-off the targeted bandwidth and complexity of increased quantizer level. NTF zero optimization technique also implemented to further reduce inband quantization noise by shaping at high frequency, which is later filtered by digital low-pass filter. Mismatch simulation results also performed for quantizer levels considering the performance degradation of the modulator. Operational amplifier (op-amp) for the front-end integrator optimized for minimum power consumption by considering low finite DC-gain, limited slew-rate, minimum required gain-bandwidth product (GBW). The proposed model simulations provided and discussed. Non-ideal effect for the proposed complete modulator CIFF structure for switched-capacitor circuit level implementation performed. The non-ideal parameters like thermal noise, sampling jitter, white noise, and switch nonlinearity also discussed. Modeling simulation results for CIFF structure with trilevel quantizer, shows that proposed modulator structure can achieve signal-to-noise ratio (SNR) of 133dB for sensor system bandwidth of 10kHz with OSR = 128

Ultra-Low Power ADCs for Space Sensors and Instruments

A 28nm 0.1V 10-bit 2kS/s Successive Approximation Register ADC design is proposed. This design opens the doors to both low supply and low power space sensors and instruments. Due to the stringent voltage supply unique challenges arise that are met with innovation in the sample switch and comparator design. These components of the ADC architecture are optimized to perform successfully at a 0.1V supply with a sample rate suitable for most sensor applications

Ultra-Low Power ADCs for Space Sensors and Instruments

A 28nm 0.1V 10-bit 2kS/s time domain ADC design is proposed. This design opens the doors to both low supply and low power space sensors and instruments. Due to the stringent voltage supply, unique challenges arise that are met with innovation in the sample switch and the quantizer design. These components of the ADC architecture are optimized to perform successfully at a 0.1V supply with a sample rate suitable for most sensor applications

Systematic Design Methodology for Successive – Approximation ADCs

Successive – Approximation ADCs are widely used in ultra – low – power applications. This paper describes a systematic design procedure for designing Successive – Approximation ADCs for biomedical sensor nodes. The proposed scheme is adopted in the design of a 12 bit 1 kS/s ADC. Implemented in 65 nm CMOS, the ADC consumes 354 nW at a sampling rate of 1 kS/s operating with 1.2 supply voltage. The achieved ENOB is 11.6, corresponding to a FoM of 114 fJ/conversion – step

A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications

A power-scalable SAR ADC for sensor applications is presented. The ADC features a reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low resolutions where noise and linearity requirements are reduced, supply voltage scaling is leveraged to further reduce the energy-per-conversion. The ADC operates up to 2 MS/s at 1 V and 5 kS/s at 0.4 V, and its power scales linearly with sample rate down to leakage levels of 53 nW at 1 V and 4 nW at 0.4 V. Leakage power-gating during a SLEEP mode in between conversions reduces total power by up to 14% at sample rates below 1 kS/s. Prototyped in a low-power 65 nm CMOS process, the ADC in 10-bit mode achieves an INL and DNL of 0.57 LSB and 0.58 LSB respectively at 0.6 V, and the Nyquist SNDR and SFDR are 55 dB and 69 dB respectively at 0.55 V and 20 kS/s. The ADC achieves an optimal FOM of 22.4 fJ/conversion-step at 0.55 V in 10-bit mode. The combined techniques of DAC resolution and voltage scaling maximize efficiency at low resolutions, resulting in an FOM that increases by only 7x over the 5-bit scaling range, improving upon a 32x degradation that would otherwise arise from truncation of bits from an ADC of fixed resolution and voltage.United States. Defense Advanced Research Projects AgencyNatural Sciences and Engineering Research Council of Canad

DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS

With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI

LOW-POWER LOW-VOLTAGE ANALOG CIRCUIT TECHNIQUES FOR WIRELESS SENSORS

This research investigates lower-power lower-voltage analog circuit techniques suitable for wireless sensor applications. Wireless sensors have been used in a wide range of applications and will become ubiquitous with the revolution of internet of things (IoT). Due to the demand of low cost, miniature desirable size and long operating cycle, passive wireless sensors which don\u27t require battery are more preferred. Such sensors harvest energy from energy sources in the environment such as radio frequency (RF) waves, vibration, thermal sources, etc. As a result, the obtained energy is very limited. This creates strong demand for low power, lower voltage circuits. The RF and analog circuits in the wireless sensor usually consume most of the power. This motivates the research presented in the dissertation. Specially, the research focuses on the design of a low power high efficiency regulator, low power Resistance to Digital Converter (RDC), low power Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with parasitic error reduction and a low power low voltage Low Dropout (LDO) regulator. This dissertation includes a low power analog circuit design for the RFID wireless sensor which consists of the energy harvest circuits (an optimized rectifier and a regulator with high current efficiency) and a sensor measurement circuit (RDC), a single end sampling SAR ADC with no error induced by the parasitic capacitance and a digital loop LDO whose line and load variation response is improved. These techniques will boost the design of the wireless sensor and they can also be used in other similar low power design

Design and Optimization of a Low Power Pressure Sensor for Wireless Biomedical Applications

A blood pressure sensor suitable for wireless biomedical applications is designed and optimized. State-of-the-art blood pressure sensors based on piezoresistive transducers in a full Wheatstone bridge configuration use low ohmic values because of relatively high sensitivity and low noise approach resulting in high power consumption. In this paper, the piezoresistance values are increased in order to reduce by one order of magnitude the power consumption in comparison with literature approaches. The microelectromechanical system (MEMS) pressure sensor, the mixed signal circuits signal conditioning circuitry, and the successive approximation register (SAR) analog-to-digital converter (ADC) are designed, optimized, and integrated in the same substrate using a commercial 1 μm CMOS technology. As result of the optimization, we obtained a digital sensor with high sensitivity, low noise (0.002 μV/Hz), and low power consumption (358 μW). Finally, the piezoresistance noise does not affect the pressure sensor application since its value is lower than half least significant bit (LSB) of the ADC