Overview of ionizing radiation effects in image sensors fabricated in a deep-submicrometer CMOS imaging technology

An overview of ionizing radiation effects in imagers manufactured in a 0.18-μm CMOS image sensor technology is presented. Fourteen types of image sensors are characterized and irradiated by a 60Co source up to 5 kGy. The differences between these 14 designs allow us to separately estimate the effect of ionizing radiation on microlenses, on low- and zero-threshold-voltage MOSFETs and on several pixel layouts using P+ guard-rings and edgeless transistors. After irradiation, wavelength dependent responsivity drops are observed. All the sensors exhibit a large dark current increase attributed to the shallow trench isolation that surrounds the photodiodes. Saturation voltage rises and readout chain gain variations are also reported. Finally, the radiation hardening perspectives resulting from this paper are discussed

High Efficiency IGBTs through Novel Three-Dimensional Modelling and New Architectures

New Insulated Gate Bipolar Transistor (IGBT) designs are reliant on simulation tools, such as Sentaurus technology computer-aided design (TCAD) models, which allow for rapid device development that could not be achieved by manufacturing prototypes due to the cost and time associated with fabrication. These simulations are, though, computationally expensive and typically most design engineers develop these TCAD models only in two dimensions. This leads to inaccuracies in the model output since manufactured transistors are inherently three-dimensional (3D). Based upon a commercial IGBT, this thesis begins by outlining the development of a 3D TCAD model using design details provided by the manufacturer. Large variations between the experimental data from the manufactured device and the simulation model lead to the discovery of widespread birds-beaking within the IGBT – an uncontrollable processing defect that the manufacturer was unaware of. This thesis presents a new simulation technique to account for this processing error while minimising computational effort and investigates the consequence of this birds-beak on the reliability of the device. The verified 3D IGBT model was also used to determine an optimum cell design that considered critical 3D effects omitted from previous studies. An extensive literature review for the Reverse-Conducting IGBT (RC-IGBT) is provided. It is shown that despite the benefits of the RC-IGBT, the device suffers from many undesirable design trade-offs that have prevented its widespread use. The RC-IGBT designs that have currently been proposed in literature, either present a trade-off in performance, an inability to be manufactured, or a requirement for a custom gate drive. This thesis presents a new RC-IGBT concept, the ‘Dual Implant SuperJunction (SJ) RC-IGBT’ that addresses these concerns and is manufacturable using current state of the art techniques. The concept and proposed manufacturing method enables, for the first time, a full SuperJunction structure to be achieved in a 1.2kV device. In addition, an investigation into a coordinated switching scheme using both a silicon IGBT and silicon-carbide MOSFET was undertaken, which aimed to improve turn-off losses within the IGBT without sacrificing on-state losses. Thermal modelling of the power devices switching under inductive load was explored as the system was optimised to use a SiC MOSFET in excess of its nominal ratings, reducing the overall system cost.EPSRC Doctoral Training Partnership scheme (grant RG75686

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes

This paper presents a summary of the main results we observed after several years of study on irradiated custom imagers manufactured using 0,18 µm CMOS processes dedicated to imaging. These results are compared to irradiated commercial sensor test results provided by the Jet Propulsion Laboratory to enlighten the differences between standard and pinned photodiode behaviors. Several types of energetic particles have been used (gamma rays, X-rays, protons and neutrons) to irradiate the studied devices. Both total ionizing dose (TID) and displacement damage effects are reported. The most sensitive parameter is still the dark current but some quantum eficiency and MOSFET characteristics changes were also observed at higher dose than those of interest for space applications. In all these degradations, the trench isolations play an important role. The consequences on radiation testing for space applications and radiation-hardening-by-design techniques are also discussed

Damascene Double Gated Transistors and Related Manufacturing Methods

This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices

Testing Methodologies for Power Electronic Devices With focus on MOSFETs and IGBTs

Metal Oxide Semiconductor Field Effect Transistor (MOSF ET s) and Insu-lated Gate Bipolar Transistor (IGBT s); both are the state-of-the-art semiconductor switching devices.In this study an in-depth study of Metal Oxide Semiconductor (MOS) physics, cell structure and electrical characterization of MOSFETs and IGBTs has been con-ducted. The aim is to achieve a further improvement on the reliability and rugged-ness of these power electronic devices using findings of the research. These power devices have an extensive industrial and domestic applications, they are the building blocks of nearly all types of power electronic circuits, control systems and advanced digital data storages, laptop and phone chargers, motor drives in electric vehicle, PV converters, Wind converters, industrial heaters. Power electronic monitoring systems including DC to DC converters, DC to AC inverters, AC to DC rectifiers and AC to AC converter.Silvaco simulation and MATLAB modeling enabled the research to gain a vivid understanding of device operation MOS physics and all relevant electrical charac-teristics. The practical experiment side of the research includes high power semi-conductor devices characterization; testing of fabricated discrete devices comprising:(200V, 40A Silicon MOSFET; 1.2KV, 19A Silicon Carbide MOSFET; 600V, 20A and 40A Silicon IGBT; 1.2KV, 25A Silicon IGBT). Consequently, the research work gained an insight to the semiconductor switching latest technologies that are useful for the optimization consideration of power electronic devices. Observations from published journals enabled to see the existing relevant research gaps and works car-ried out by other scientists around this field area. Silicon is the working material for this master’s by research thesis. Moreover, this paper also looks into the great benefits of using silicon-carbide as a material for the next generation technological innovations.Therefore, this research contributes towards device optimization in the following way:Firstly, at a single cell design level. Shielded trench gate geometry architecture outperforms planar gate structure. Secondly, fabricating using a Wide-band-gap material (WBG) enhances device performance greatly

Moving towards high carrier mobility power devices in silicon and silicon carbide

This thesis reports on recent progress regarding the characterization, design and fabrication of modern power semiconductor devices in Silicon (Si) as well as in the promising wide band gap material Silicon Carbide (SiC). Up to now, state of the art power devices are architectured on the basis of monocrystalline Si-wafers. This is due to the high material quality of Si in combination with the availability of a mature and reliable fabrication technology based on a well-established process library. However, more and more sophisticated device designs such as e.g. the Super-Junction (SJ) architecture require an increasing number of fabrication steps therefore increasing the amount of possible sources of error. Further, more complex three-dimensional dopant distribution profiles are needed for the devices to withstand the high blocking voltage demands of current power semiconductor applications when operated in reverse direction. This dopant distribution has to be monitored, at least for control samples, after implantation, after further thermal processes and during the duty cycle. To ensure reliable device operation, in particular for charge compensated devices, this monitoring or mapping has to be performed locally with high precision and sensitivity. In this work complementary Scanning Probe Microscopy (SPM) based methods like: Kelvin Probe Force Microscopy (KPFM), Scanning Capacitance Force Microscopy (SCFM) and Scanning Spreading Resistance Microscopy (SSRM) have been explored for a precise monitoring of carrier concentration profiles. This is due to the fact that so far none of the established industrial techniques such as e.g. Secondary Ion Mass Spectrometry (SIMS) or Spreading Resistance Probe (SRP) was mature enough to simultaneously full-fill all the major requirements of the semiconductor industry in terms of spatial resolution, sensitivity, reproducibility and the ability to quantify dopant concentrations. Further, SIMS is probing the chemical composition rather than the charge carrier distribution. To ‘look inside’ the inhomogeneously doped sample, smooth device cross-sections need to be prepared in a reliable manner and without distorting the ‘as implanted/activated’ dopant profile. In this way artefacts arising from a topographic signal can be ruled out. For Si the easiest way would be to cleave the wafer along a certain crystallographic direction. However, since the SPM methods presented here shall serve as a characterization tool with a general validity another approach that is also suitable for different crystal structures and materials with a hardness close to diamond had to be found. For this reason a chemical mechanical polishing (CMP) procedure had been developed at PSI. This process was optimized for maintaining a low surface state density as it is important to avoid a complete pinning of the Fermi level for the KPFM measurements. The subsequent Atomic Force Microscopy (AFM) imaging has been performed in collaboration with the experts in the research group of Prof. Ernst Meyer at the University of Basel. Within this project it has been demonstrated that every SPM derived method is capable to qualitatively map carrier concentrations down to an unprecedented low regime. However, a difference regarding the lateral resolution was observed which can be understood by different information depths depending on the underlying physical quantity to be measured together with an imperfect surface preparation which is leading to an accumulation or depletion of defects at the surface. The most critical technique in that sense - due to its high surface sensitivity - is the contact potential difference measurement that is utilized by KPFM to draw conclusions on the carrier concentration. By laser illumination of the sample during the KPFM experiment a Surface Photo Voltage (SPV) occurs in a surface near layer with a thickness in the order of the minority carrier diffusion length. Thus, the surface sensitivity is reduced and the signal distortion due to the unfavourable influence of surface defects gets less pronounced. Even though SCFM is also based on the detection of the electrostatic force that develops between the tip and the sample, this method is less affected by the surface because it is probing a different physical quantity, namely the total capacitance of the rather extended oxide/depletion layer capacitance system. Furthermore, the magnitude of the SCFM signal scales inverse proportionally with respect to the carrier concentration, hence this method is theoretically offering the highest sensitivity in the low concentration regime. Nevertheless, a quantification scheme for this technique is still in development and further work on locally acquired spectroscopic capacitance-voltage (C-V ) measurements is needed towards a reliable quantification procedure. The third SPM derived method SSRM, is operated in contact mode under high normal forces to ensure that the spreading resistance is the dominant resistance contribution for the current flowing between the tip and the sample. Under these circumstances the local carrier concentration and its impact on the magnitude and the sign of the output current can be investigated in a very accurate and quantitative manner. Beside that, the high mechanical forces cause an abrasive motion of the tip while scanning the sample. This feature is beneficial in two ways: on one hand the native oxide and the underlying defect-rich surface layer are removed while on the other hand a phase transformation of a tiny sample volume just below the tip occurs which locally decreases the resistivity and increases the spatial resolution. Hence, the SSRM technique is showing a high degree of reproducibility and is therefore ideal for quantitative studies. As mentioned above the considerable complexity of the fabrication process and the limited material properties of Si in terms of a high critical electric field and a high thermal conductivity accelerated the search for novel substrates for power semiconductor applications. Beside offering an order of magnitude higher critical electric field due to its wide band gap (WBG), SiC also attracted attention since it can be thermally oxidized resulting in a silicon dioxide (SiO2) layer as its native oxide. Therefore, this material has been classified as most promising and theoretical improvements of a - by a factor of 400 - lower ON-resistance have been calculated. However, to date SiC devices are facing other problems related to the engineering of dopant profiles and the more complex nature of the oxidation process which limit their performance and hinder their large-scale commercialization. The incorporation of a specific dopant distribution in SiC is most effectively done by an ion implantation process followed by a high temperature annealing step which is needed to restore the crystal structure after implantation-induced damage and to electronically activate the dopant atoms. This is caused by the fact that in SiC due to its wide band gap of 2.4-3.2 eV (depending on its poly-type) basically no dopant diffusion at reasonable thermal budgets occurs. Notably, not all of these dopant atoms are ionized and contribute to the electric conduction within the semiconductor. Especially the hole concentration p and the acceptor concentration NA can differ significantly in SiC due to the large ionization energies. Hence it has to be taken into account that the final performance of a SiC power device might be inferior to the expected performance from the implantation parameters. This behaviour is in clear contrast to Si where at room temperature basically all donor and acceptor atoms are ionized and no further differentiation between the dopant and the carrier (electronically active dopant) profile has to be made. The above mentioned SPM methods are sensitive to the carrier rather than to the dopant profile and within this work it has been demonstrated that e.g. the p-doped guard ring structure of a SiC Schottky diode which is shielding the metal contact from high electric fields that occur under reverse bias operation can be resolved. Another challenge for SiC Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are low carrier mobilities inside the thin conducting channel at the semiconductor/oxide interface and threshold voltage instabilities. Due to the more complex nature of the oxidation process which requires the removal of carbon atoms in the form of CO or CO2 from the SiC crystal the SiC/SiO2 interface is showing a high density of interface trap states that act as scattering centres and degrade the carrier mobility. Hence, experimentally observed charge carrier mobilities are by a factor of 10 below the theoretical value of the bulk material. Thereby the ON-resistance which is inverse proportional to the mobility is increased which is leading to a higher amount of power dissipation in the ON-state of the device. Unsurprisingly, a lot of research effort has been triggered in this direction resulting in breakthrough called post-oxidation annealing (POA) under gaseous ambients. Nitrogen and phosphorous based chemistries have shown a passivating effect on the density of interface trap states. However, the origin of this mechanism is not yet fully understood. A possible explanation is a counter-doping effect within a thin layer at the semiconductor surface. A second - maybe easier - pathway to increase the channel mobility is the utilization of the crystal anisotropy. The mobility strongly depends on the orientation of the channel with respect to the crystallographic axis. Among them the 1120 direction exhibits the highest mobility. In the here presented project this approach has been utilized to improve the device performance without changing too many parameters regarding the oxidation or post-oxidation treatments at the same time. In this case the remaining challenge was to develop an etching process which is able to etch several um deep trenches into SiC and to precisely control the shape of the resulting trench profile. It has been demonstrated that sharp corners that would cause field crowding at the edges can be eliminated by the usage of very small DC biases applied between the electrode of the plasma chamber and the substrate. Furthermore, the steepness of the sidewalls could be controlled by the composition of the plasma gas flows. Contrary to previous reports we found that the addition of oxygen to the dry etching process is not helping to avoid microtrenching. Either a pure SF6 based process or an SF6 based process with the addition of Ar have shown the best results. With this success a full manufacturing cycle for a nanoscale trench MOSFET has been designed

Investigation of FACTS devices to improve power quality in distribution networks

Flexible AC transmission system (FACTS) technologies are power electronic solutions that improve power transmission through enhanced power transfer volume and stability, and resolve quality and reliability issues in distribution networks carrying sensitive equipment and non-linear loads. The use of FACTS in distribution systems is still in its infancy. Voltages and power ratings in distribution networks are at a level where realistic FACTS devices can be deployed. Efficient power converters and therefore loss minimisation are crucial prerequisites for deployment of FACTS devices. This thesis investigates high power semiconductor device losses in detail. Analytical closed form equations are developed for conduction loss in power devices as a function of device ratings and operating conditions. These formulae have been shown to predict losses very accurately, in line with manufacturer data. The developed formulae enable circuit designers to quickly estimate circuit losses and determine the sensitivity of those losses to device voltage and current ratings, and thus select the optimal semiconductor device for a specific application. It is shown that in the case of majority carrier devices (such as power MOSFETs), the conduction power loss (at rated current) increases linearly in relation to the varying rated current (at constant blocking voltage), but is a square root of the variable blocking voltage when rated current is fixed. For minority carrier devices (such as a pin diode or IGBT), a similar relationship is observed for varying current, however where the blocking voltage is altered, power losses are derived as a square root with an offset (from the origin). Finally, this thesis conducts a power loss-oriented evaluation of cascade type multilevel converters suited to reactive power compensation in 11kV and 33kV systems. The cascade cell converter is constructed from a series arrangement of cell modules. Two prospective structures of cascade type converters were compared as a case study: the traditional type which uses equal-sized cells in its chain, and a second with a ternary relationship between its dc-link voltages. Modelling (at 81 and 27 levels) was carried out under steady state conditions, with simplified models based on the switching function and using standard circuit simulators. A detailed survey of non punch through (NPT) and punch through (PT) IGBTs was completed for the purpose of designing the two cascaded converters. Results show that conduction losses are dominant in both types of converters in NPT and PT IGBTs for 11kV and 33kV systems. The equal-sized converter is only likely to be useful in one case (27-levels in the 33kV system). The ternary-sequence converter produces lower losses in all other cases, and this is especially noticeable for the 81-level converter operating in an 11kV network

AC solar cells: An embedded "all in one" PV power system

Journal ArticlePower converters constructed from discrete components are difficult to mass produce, and the installation involves a significant labor cost to have the proper interconnection among the panel, inverter and the grid. These facts indicate that the present PV technology may not be able to address the challenges involved in reaching the DOE target of $1/W. Therefore, a paradigm shift in the design of the entire PV power system is needed to reach this goal. In order to increase the converter reliability and watts/$, the active and passive elements of a power converter (especially capacitors and active switches such as MOSFETs, JFETs or IGBTs) could be embedded on the same substrate material used for fabricating the p-n junctions in the photovoltaic panel. To the knowledge of the author, there is no prior work in cell level power conversion, and therefore, this project idea could be considered as an "Out of the box" kind. A novel fabrication process is proposed in this paper demonstrating the integration of PV cells and two major components needed to build a power converter. Because of the cell level power conversion, PV panels constructed from these cells are likely to be immune to partial shading and hot-spot effects. The end goal of this research is to produce 120V/240V ac output directly from the panel. An extremely accurate device simulator (*Silvaco Athena/Atlas) was used to generate reasonably accurate characteristics of the proposed PV system