Millimeter-Wave Concurrent Dual-Band BiCMOS RFIC Transmitter for Radar and Communication Systems

This dissertation presents new circuit architectures and techniques for improving the performance of several key BiCMOS RFIC building blocks used in radar and wireless communication systems operating up to millimeter-wave frequencies, and the development of an advanced, low-cost and miniature millimeter-wave concurrent dual-band transmitter for short-range, high-resolution radar and high-rate communication systems. A new type of low-power active balun consisting of a common emitter amplifier with degenerative inductor and a common collector amplifier is proposed. The parasitic neutralization and compensation techniques are used to keep the balun well balanced at very high frequencies and across an ultra-wide bandwidth. A novel RF switch architecture with ultra-high isolation and possible gain is proposed, analyzed and demonstrated. The new RF switch architecture achieves an ultra-high isolation through implementation of a new RF leaking cancellation technique. A new class of concurrent dual-band impedance matching networks and technique for synthesizing them are presented together with a 25.5/37-GHz concurrent dual-band PA. These matching networks enable simultaneous matching of two arbitrary loads to two arbitrary sources at two different frequencies, utilizing the impedance-equivalence properties of LC networks that any LC network can be equivalent to an inductor, capacitor, open or short at different frequencies. K- and Ka-band ultra-low-leakage RF-pulse formers capable of producing very narrow RF pulses in the order of 200 ps with small rising and falling time for short-range high-resolution radar and high-data-rate communication systems are also developed. The complete transmitter exhibiting unique characteristics obtained from capabilities of producing very narrow and tunable RF pulses with extremely RF leakage and working concurrently in dual bands at 24.5 and 35 GHz was designed. Capability of generating narrow and tunable RF pulses allows the radar system to flexibly work at high and multiple range resolutions. The extremely low RF leakage allows the transmitter to share one antenna system with receiver, turn on the PA at all time, comply the transmitting spectrum requirements, increase the system dynamic range, avoid harming to other systems; hence improving system size, cost and performance. High data-rate in communication systems is achieved as the consequence of transmitting very narrow RF pulses at high rates. In addition, the dissertation demonstrates a design approach for low chip-area, cost and power consumption systems in which a single dual-band component (power amplifier) is designed to operate with two RF signals simultaneously

Wideband Watt-Level Spatial Power-Combined Power Amplifier in SiGe BiCMOS Technology for Efficient mm-Wave Array Transmitters

The continued demand for high-speed wireless communications is driving the development of integrated high-power transmitters at millimeter wave (mm-Wave) frequencies. Si-based technologies allow achieving a high level of integration but usually provide insufficient generated RF power to compensate for the increased propagation and material losses at mm-Wave bands due to the relatively low breakdown voltage of their devices. This problem can be reduced significantly if one could combine the power of multiple active devices on each antenna element. However, conventional on-chip power combining networks have inherently high insertion losses reducing transmitter efficiency and limiting its maximum achievable output power.This work presents a non-conventional design approach for mm-Wave Si-based Watt-level power amplifiers that is based on novel power-combining architecture, where an array of parallel custom PA-cells suited on the same chip is interfaced to a single substrate integrated waveguide (to be a part of an antenna element). This allows one to directly excite TEm0 waveguide modes with high power through spatial power combining functionality, obviating the need for intermediate and potentially lossy on-chip power combiners. The proposed solution offers wide impedance bandwidth (50%) and low insertion losses (0.4 dB), which are virtually independent from the number of interfaced PA-cells. The work evaluates the scalability bounds of the architecture as well as discusses the critical effects of coupled non-identical PA-cells, which are efficiently reduced by employing on-chip isolation load resistors.The proposed architecture has been demonstrated through an example of the combined PA with four differential cascode PA-cells suited on the same chip, which is flip-chip interconnected to the combiner placed on a laminate. This design is implemented in a 0.25 um SiGe BiCMOS technology. The PA-cell has a wideband performance (38.6%) with both high peak efficiency (30%) and high saturated output power (24.9 dBm), which is the highest reported output power level obtained without the use of circuit-level power combining in Si-based technologies at Ka-band. In order to achieve the optimal system-level performance of the combined PA, an EM-circuit-thermal optimization flow has been proposed, which accounts for various multiphysics effects occurring in the joint structure. The final PA achieves the peak PAE of 26.7% in combination with 30.8 dBm maximum saturated output power, which is the highest achievable output power in practical applications, where the 50-Ohms load is placed on a laminate. The high efficiency (>20%) and output power (>29.8 dBm) over a wide frequency range (30%) exceed the state-of-the-art in Si-based PAs

Microwave and Millimeter-Wave Multi-Band Power Amplifiers, Power Combining Networks, and Transmitter Front-End in Silicon Germanium BiCMOS Technology

This dissertation presents new circuit architectures and techniques for designing high performance microwave and millimeter-wave circuits using 0.18-µm SiGe BiCMOS process for advanced wireless communication and sensing systems. The high performance single- and multi-band power amplifiers working in microwave and millimeter-wave frequency ranges are proposed. A 10-19, 23-39, and 33-40 GHz concurrent tri-band power amplifier in the respective Ku-, K-, and Ka-band using the distributed amplifier structure is presented first. Instead of utilizing multi-band matching networks, this amplifier is realized based on distributed amplifier structure and two active notch filters employed at each gain cell to form tri-band response. In addition, a power amplifier operating across the entire K-band is proposed. By employing lumped-element Wilkinson power divider and combiner, it produces high output power, high gain, and power added efficiency characteristics over broadband due to its inherent low-pass filtering response. Moreover, a highly integrated V-band power amplifier is presented. This power amplifier consists of four medium unit power cells combined with a four-way parallel power combining network. Secondly, microwave and millimeter-wave power combining and dividing networks are proposed. A wideband power divider and combiner operating up to 67 GHz is developed by adopting capacitive loading slow-wave transmission line to reduce size as well as insertion loss. Also, two-way and 16-way 24/60 GHz dual-band power divider networks in the K/V-band are proposed. The two-way dual-band power divider is realized with a slow-wave transmission line and two shunt connected LC resonators in order to minimize the chip size as well as insertion loss. Furthermore, a 16-way dual-band power dividing and combining network is developed for a dual-band 24/60 GHz 4×4 array system. This network incorporates a two-way dual-band power divider, lumped-element based Wilkinson power dividers, and multi-section transmission line based Wilkinson structures. Finally, a K-/V-band dual-band transmitter front-end is proposed. To realize the transmitter, a diplexer with good diplexing performance and K- and V-band variable gain amplifiers having low phase variation with gain tuning are designed. The transmitter is integrated with two diplexers, K- and V-band variable gain amplifiers, and two power amplifiers resulting in high gain, high output power, and low-phase variation with all gain control stages

KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

Blocker Tolerant Radio Architectures

Future radio platforms have to be inexpensive and deal with a variety of co- existence issues. The technology trend during the last few years is towards system- on-chip (SoC) that is able to process multiple standards re-using most of the digital resources. A major bottle-neck to this approach is the co-existence of these standards operating at different frequency bands that are hitting the receiver front-end. So the current research is focused on the power, area and performance optimization of various circuit building blocks of a radio for current and incoming standards. Firstly, a linearization technique for low noise amplifiers (LNAs) called, Robust Derivative Superposition (RDS) method is proposed. RDS technique is insensitive to Process Voltage and Temperature (P.V.T.) variations and is validated with two low noise transconductance amplifier (LNTA) designs in 0.18µm CMOS technology. Measurement results from 5 dies of a resistive terminated LNTA shows that the pro- posed method improves IM3 over 20dB for input power up to -18dBm, and improves IIP_(3) by 10dB. A 2V inductor-less broadband 0.3 to 2.8GHz balun-LNTA employing the proposed RDS linearization technique was designed and measured. It achieves noise figure of 6.5dB, IIP3 of 16.8dBm, and P1dB of 0.5dBm having a power consumption of 14.2mW. The balun LNTA occupies an active area of 0.06mm2. Secondly, the design of two high linearity, inductor-less, broadband LNTAs employing noise and distortion cancellation techniques is presented. Main design issues and the performance trade-offs of the circuits are discussed. In the fully differential architecture, the first LNTA covers 0.1-2GHz bandwidth and achieves a minimum noise figure (NFmin) of 3dB, IIP_(3) of 10dBm and a P_(1dB) of 0dBm while dissipating 30.2mW. The 2^(nd) low power bulk driven LNTA with 16mW power consumption achieves NFmin of 3.4dB, IIP3 of 11dBm and 0.1-3GHz bandwidth. Each LNTA occupy an active area of 0.06mm2 in 45nm CMOS. Thirdly, a continuous-time low-pass ∆ΣADC equipped with design techniques to provide robustness against loop saturation due to blockers is presented. Loop over- load detection and correction is employed to improve the ADC’s tolerance to blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADC’s blocker tolerance, a minimally-invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. An ADC prototype is implemented in a 90nm CMOS technology and experimentally it achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500MHz and 17.1mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5dBFS while the conventional feed-forward modulator becomes unstable at -23.5dBFS of blocker power. The proposed blocker rejection techniques are minimally-invasive and take less than 0.3µsec to settle after a strong agile blocker appears. Finally, a new radio partitioning methodology that gives robust analog and mixed signal radio development in scaled technology for SoC integration, and the co-design of RF FEM-antenna system is presented. Based on the proposed methodology, a CMOS RF front-end module (FEM) with power amplifier (PA), LNA and transmit/receive switch, co-designed with antenna is implemented. The RF FEM circuit is implemented in a 32nm CMOS technology. Post extracted simulations show a noise figure < 2.5dB, S_(21) of 14dB, IIP3 of 7dBm and P1dB of -8dBm for the receiver. Total power consumption of the receiver is 11.8mW from a 1V supply. On the trans- mitter side, PA achieves peak RF output power of 22.34dBm with peak power added efficiency (PAE) of 65% and PAE of 33% with linearization at -6dB power back off. Simulations show an efficiency of 80% for the miniaturized dipole antenna

Push-Pull Based High Efficiency and High Power Broadband Power Amplifiers for Wireless Base Stations

The monthly data throughput by 2021 is forecasted to be ten times that of December 2015. As a result of the on going dramatic increase in demand, service providers are assigned new frequency bands to accommodate more channels to carry more data. However, the usable part of the spectrum is a limited resource so modern communication signals were designed to be more spectrally efficient to send more bits over the same channel bandwidth. However, these spectrally efficient signals have high PAPR. The immediate reaction to these changes was to add additional RF front-end branches to accommodate the new frequency bands. Initially, the PAs used at the time were not optimized for back-off efficiency and where operating at low efficiency which caused significant increase in heat generation for the same average power produced which in turn increased cooling costs and reduced the life time of the PA. After the introduction of back-off efficiency enhancement techniques the PAs became more efficient however they were limited in bandwidth which is typically 10-15%. This work focuses on reducing the redundancy of power amplifiers in communication base stations while maintaining high back-off efficiency. After exploring the literature to understand the limitations of current implementations, it was found that the push-pull topology is often used at low frequency in broadband high power PAs. In the absence of a complimentary transistor pairs the push-pull implantation requires the use of balanced to unbalanced (balun) transformers. Various balun implantations were hence investigated to identify the most suitable option for broadband planar implementation. As a result, a methodology was proposed to co-design the balun and the matching network in order to have better control over the harmonic impedance. An 85 W push-pull PA was then designed based on the proposed methodology with a multi-octave bandwidth as a demonstration of the broadband potential of push-pull PAs at RF frequencies. Next, the two most popular techniques for back-off efficiency enhancement, i.e., ET and load modulation, were studied and the principle of load modulation was found to be more suitable for broadband signal transmission. The Doherty architecture is the most common implementation of load modulation and it comes in two basic variations, the PCL and SCL DPAs. The original architecture concepts are not only band limited but also ill-suited for high frequency designs where the transistors' parasitics introduce significant effect. However, later literature expanded on the original concept of the PCL variation which provided the needed flexibility for wider bandwidth implementations at a higher frequency. Using the broadband implementation and the co-design methodology two push-pull amplifiers were used in a PCL DPA topology and demonstrated that the push-pull utilization doesn't have a significant impact on the bandwidth of the output combiner as an octave bandwidth was achieved with the use of digital Doherty. Lastly, the thesis proposes a new approach for designing high power DPAs with extended bandwidth. It starts with a generic SCL DPA architecture to derive the equations that relate its underlying combiner's ABCD parameters to the transistor's optimum impedance and load impedance. These equations featured the possibility of significantly increasing the load impedance in SCL DPA compared to the one of the popular PCL DPA architecture. This is particularly beneficial when targeting very high power DPAs for macro-cell base stations and broadcast applications where very low load impedance can seriously complicate the design and limit the achievable bandwidth. To further maximize the load impedance increase, the proposed SCL DPA uses a push-pull topology for the main and peaking amplifier stages. A low-loss planar balanced to unbalanced transformer (balun) combiner network is then utilized to realize the SCL DPA combining. The proposed approach was finally applied to design a proof-of-concept 350 W SCL DPA which operates over the band spanning from 720 to 980 MHz. The prototype demonstrated a peak output power of about 55 dBm over a 30% FBW with a 6 dB back-off efficiency, measured using pulsed signal, between 46.6% and 54.6%. Furthermore, the modulated signal based measurement results confirmed the linearizability of the SCL DPA prototype while maintaining a back-off efficiency over 50% for a 7.1 dB peak to average power ratio signal

Integrated Circuit and Antenna Technology for Millimeter-wave Phased Array Radio Front-end

Ever growing demands for higher data rate and bandwidth are pushing extremely high data rate wireless applications to millimeter-wave band (30-300GHz), where sufficient bandwidth is available and high data rate wireless can be achieved without using complex modulation schemes. In addition to the communication applications, millimeter-wave band has enabled novel short range and long range radar sensors for automotive as well as high resolution imaging systems for medical and security. Small size, high gain antennas, unlicensed and worldwide availability of released bands for communication and a number of other applications are other advantages of the millimeter-wave band. The major obstacle for the wide deployment of commercial wireless and radar systems in this frequency range is the high cost and bulky nature of existing GaAs- and InP-based solutions. In recent years, with the rapid scaling and development of the silicon-based integrated circuit technologies such as CMOS and SiGe, low cost technologies have shown acceptable millimeter-wave performance, which can enable highly integrated millimeter-wave radio devices and reduce the cost significantly. Furthermore, at this range of frequencies, on-chip antenna becomes feasible and can be considered as an attractive solution that can further reduce the cost and complexity of the radio package. The propagation channel challenges for the realization of low cost and reliable silicon-based communication devices at millimeter-wave band are severe path loss as well as shadowing loss of human body. Silicon technology challenges are low-Q passive components, low breakdown voltage of active devices, and low efficiency of on-chip antennas. The main objective of this thesis is to investigate and to develop antenna and front-end for cost-effective silicon based millimeter-wave phased array radio architectures that can address above challenges for short range, high data rate wireless communication as well as radar applications. Although the proposed concepts and the results obtained in this research are general, as an important example, the application focus in this research is placed on the radio aspects of emerging 60 GHz communication system. For this particular but extremely important case, various aspects of the technology including standard, architecture, antenna options and indoor propagation channel at presence of a human body are studied. On-chip dielectric resonator antenna as a radiation efficiency improvement technique for an on-chip antenna on low resistivity silicon is presented, developed and proved by measurement. Radiation efficiency of about 50% was measured which is a significant improvement in the radiation efficiency of on-chip antennas. Also as a further step, integration of the proposed high efficiency antenna with an amplifier in transmit and receive configurations at 30 GHz is successfully demonstrated. For the implementation of a low cost millimeter-wave array antenna, miniaturized, and efficient antenna structures in a new integrated passive device technology using high resistivity silicon are designed and developed. Front-end circuit blocks such as variable gain LNA, continuous passive and active phase shifters are investigated, designed and developed for a 60GHz phased array radio in CMOS technology. Finally, two-element CMOS phased array front-ends based on passive and active phase shifting architectures are proposed, developed and compared

Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results

Architectures and Integrated Circuits for Efficient, High-power "Digital'' Transmitters for Millimeter-wave Applications

This thesis presents architectures and integrated circuits for the implementation of energy-efficient, high-power "digital'' transmitters to realize high-speed long-haul links at millimeter-wave frequencies in nano-scale silicon-based processes

A Novel Power-Efficient Wireless Multi-channel Recording System for the Telemonitoring of Electroencephalography (EEG)

This research introduces the development of a novel EEG recording system that is modular, batteryless, and wireless (untethered) with the supporting theoretical foundation in wireless communications and related design elements and circuitry. Its modular construct overcomes the EEG scaling problem and makes it easier for reconfiguring the hardware design in terms of the number and placement of electrodes and type of standard EEG system contemplated for use. In this development, portability, lightweight, and applicability to other clinical applications that rely on EEG data are sought. Due to printer tolerance, the 3D printed cap consists of 61 electrode placements. This recording capacity can however extend from 21 (as in the international 10-20 systems) up to 61 EEG channels at sample rates ranging from 250 to 1000 Hz and the transfer of the raw EEG signal using a standard allocated frequency as a data carrier. The main objectives of this dissertation are to (1) eliminate the need for heavy mounted batteries, (2) overcome the requirement for bulky power systems, and (3) avoid the use of data cables to untether the EEG system from the subject for a more practical and less restrictive setting. Unpredictability and temporal variations of the EEG input make developing a battery-free and cable-free EEG reading device challenging. Professional high-quality and high-resolution analog front ends are required to capture non-stationary EEG signals at microvolt levels. The primary components of the proposed setup are the wireless power transmission unit, which consists of a power amplifier, highly efficient resonant-inductive link, rectification, regulation, and power management units, as well as the analog front end, which consists of an analog to digital converter, pre-amplification unit, filtering unit, host microprocessor, and the wireless communication unit. These must all be compatible with the rest of the system and must use the least amount of power possible while minimizing the presence of noise and the attenuation of the recorded signal A highly efficient resonant-inductive coupling link is developed to decrease power transmission dissipation. Magnetized materials were utilized to steer electromagnetic flux and decrease route and medium loss while transmitting the required energy with low dissipation. Signal pre-amplification is handled by the front-end active electrodes. Standard bio-amplifier design approaches are combined to accomplish this purpose, and a thorough investigation of the optimum ADC, microcontroller, and transceiver units has been carried out. We can minimize overall system weight and power consumption by employing battery-less and cable-free EEG readout system designs, consequently giving patients more comfort and freedom of movement. Similarly, the solutions are designed to match the performance of medical-grade equipment. The captured electrical impulses using the proposed setup can be stored for various uses, including classification, prediction, 3D source localization, and for monitoring and diagnosing different brain disorders. All the proposed designs and supporting mathematical derivations were validated through empirical and software-simulated experiments. Many of the proposed designs, including the 3D head cap, the wireless power transmission unit, and the pre-amplification unit, are already fabricated, and the schematic circuits and simulation results were based on Spice, Altium, and high-frequency structure simulator (HFSS) software. The fully integrated head cap to be fabricated would require embedding the active electrodes into the 3D headset and applying current technological advances to miniaturize some of the design elements developed in this dissertation