Optimization Opportunities in RRAM-based FPGA Architectures

Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures typically avoiding the use of large multiplexers. Resistive Random Access Memory (RRAM)- based multiplexers, built with one-level structure, have a unique advantage over SRAM-based multiplexers: their ideal delay is independent from the input size. This property allows RRAM-based FPGA architectures to use larger multiplexers than their SRAM-based counterparts, without generating any delay overhead. In this paper, by carefully considering the properties of RRAM multiplexers, we assess that current state-of-art architectural parameters for SRAM-based FPGAs cannot preserve optimality in the context of RRAM-based FPGAs. As a result, we propose that in RRAM-based FPGAs, (a) the routing tracks should be interconnected to Look-Up Table (LUT) inputs via a one-level crossbar, instead of through Connection Blocks and local routing; (b) the Switch Blocks should employ larger multiplexers; (c) length-2 wires should be used instead of length-4 wires. When operated in nominal voltage, the proposed RRAM-based FPGA architecture reduces area by 26%, delay by 39% and channel width by 13%, as compared to a SRAM-based FPGA with a classical architecture. When operated in the near-Vt regime, the proposed RRAM-based FPGA architecture improves Area-Delay Product by 42% and Power-Delay Product by 5x as compared to a classical SRAM-based FPGA at nominal voltage

Caracterização de amplificador de transcondutância diferencial de diferenças baseada em inversores CMOS

This dissertation presents the Differential Transconductance Differences Amplifier (FDDTA) architecture based on CMOS inverters. Designed on a 130 nm CMOS process, it operates in weak inversion when supplied with 0.25 V. Furthermore, FDDTA does not require supplemental external calibration circuitry such as bias current or voltage sources as it relies on the distributed layout technique that intrinsically matches CMOS inverters. For analytical purposes, we performed a detailed investigation that describes all the concepts and the entire functioning of the FDDTA architecture.Esta dissertação apresenta a arquitetura de amplificador de transcondutância diferencial de diferenças (FDDTA) baseada em inversores CMOS. Projetado em um processo CMOS de 130 nm, opera em inversão fraca quando alimentado com 0,25 V. Além disso, o FDDTA não requer circuito de calibração externa suplementar, como fontes de corrente ou tensão de polarização, uma vez que depende da técnica de layout distribuído que casa intrinsecamente aos inversores CMOS. Para fins analíticos, realizamos uma investigação detalhada que descreve todos os conceitos e todo o funcionamento da arquitetura do FDDTA

7° Jornadas ITEE 2023

En esta publicación se reúnen los trabajos y resúmenes extendidos presentados en las VII Jornadas de Investigación, Transferencia, Extensión y Enseñanza (ITEE), de la Facultad de Ingeniería de la Universidad Nacional de La Plata, organizadas por la Secretaría de Investigación y Transferencia de dicha facultad, que tuvieron lugar entre el 25 y el 27 de abril de 2023.Facultad de Ingenierí