Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Adaptive Suppression of Interfering Signals in Communication Systems

The growth in the number of wireless devices and applications underscores the need for characterizing and mitigating interference induced problems such as distortion and blocking. A typical interference scenario involves the detection of a small amplitude signal of interest (SOI) in the presence of a large amplitude interfering signal; it is desirable to attenuate the interfering signal while preserving the integrity of SOI and an appropriate dynamic range. If the frequency of the interfering signal varies or is unknown, an adaptive notch function must be applied in order to maintain adequate attenuation. This work explores the performance space of a phase cancellation technique used in implementing the desired notch function for communication systems in the 1-3 GHz frequency range. A system level model constructed with MATLAB and related simulation results assist in building the theoretical foundation for setting performance bounds on the implemented solution and deriving hardware specifications for the RF notch subsystem devices. Simulations and measurements are presented for a Low Noise Amplifer (LNA), voltage variable attenuators, bandpass filters and phase shifters. Ultimately, full system tests provide a measure of merit for this work as well as invaluable lessons learned. The emphasis of this project is the on-wafer LNA measurements, dependence of IC system performance on mismatches and overall system performance tests. Where possible, predictions are plotted alongside measured data. The reasonable match between the two validates system and component models and more than compensates for the painstaking modeling efforts. Most importantly, using the signal to interferer ratio (SIR) as a figure of merit, experimental results demonstrate up to 58 dB of SIR improvement. This number represents a remarkable advancement in interference rejection at RF or microwave frequencies

Frequency Tunable Magnetostatic Wave Filters With Zero Static Power Magnetic Biasing Circuitry

A single tunable filter can reduce the complexity, loss, and size when compared to switchable filter banks and enable new applications. Although magnetostatic wave tunable filters offer broad and continuous frequency tuning and high-quality factor (Q-factor), they consume high power and require large electromagnets to alter the magnetostatic wave velocity for filter frequency tuning. Here, we demonstrate miniature and high selectivity magnetostatic wave tunable filters with zero static power realized in Yttrium Iron Garnet thin films. The center frequency can be tuned via current pulses applied to a magnetic bias assembly from 3.36 GHz to 11.09 GHz with an insertion loss of 3.2 dB to 5.1 dB and out-of-band third order input intercept point (IIP3) of 41 to 44 dBm. Overall, the adaptability, wide frequency tuning range, and zero static power consumption of the tunable filter position it as a critical technology, effectively addressing challenges in broadband ADCs, RF transceivers, broadband digital phased array antennas, and interference mitigation in 5G and 6G networks. Broadly frequency tunable, high selectivity filters open new avenues for more efficient and dynamic RF front ends, ensuring optimal performance and seamless communication in the ever-evolving landscape of modern wireless technologies.Comment: The main manuscript contains 6918 words and 5 figures comprising 15 panels in total. The supplementary document consists of 14 Supplementary Notes and 30 Supplementary Figure

Circuits and architectures for the implementation of broadband channelizers

Broadband spectrum channelizers sub-divide a broadband input spectrum into multiple sub-bands, where each of the sub-bands is down-converted and further processed at baseband. These designs can help to relax baseband design specifications. For example, baseband analog-to-digital converters (ADCs) that process the sub-bands at the channelizer output see only a part of the incident spectrum. The sampling frequency, and potentially the dynamic range of each sub-band ADC can thus be relaxed, compared to the case where a single ADC is used to digitize the full spectrum. Spectrum channelizers can be used for multiple applications. These designs can be used as general-purpose hybrid frequency-and-time domain ADCs. The designs can also be employed for spectrum analysis, as well as for wireless communication applications. In this dissertation, two circuit techniques for the implementation of broadband channelizers are proposed. A frequency-translational feedback-based interference canceler for attenuating large interferers at the output of the front-end low-noise amplifier (LNA) of a channelizer is shown. The design uses harmonic rejection mixers (HRMs) with embedded frequency synthesis capability. While channelizers reduce the bandwidth and potentially the dynamic range of the baseband ADCs, the analog signal paths in the channelizer can be broadband. Consequently the dynamic range required of the analog section of a sub-band path can still be limited by the presence of large signals in other, potentially distant parts of the spectrum. The demonstrated design is useful for relaxing the dynamic range requirement of the analog section that follows the front-end LNA in a channelizer. Reduction of the harmonic response and the frequency synthesizer tuning-range is also achieved in this design. Second, a two-stage HRM is proposed which shares the same bias current between the RF and baseband stages, thus reducing the power consumption. Issues arising from bias-current sharing, such as the 1/f noise of the RF stage and potential degradation of the 2nd harmonic response are identified, and circuit techniques are introduced to mitigate these potential degradation mechanisms.Electrical and Computer Engineerin

RF and Millimeter-wave Techniques to Improve Scalability and Efficiency of Digital Beamforming Arrays

Spectrum overcrowding, ever increasing demand for high data rate and increased mobility requirements are three major challenges 5G-technology is trying to address. In this thesis I start with a RF front-end technique that deals with blocker interference arising from spectrum overcrowding both across frequency bands and within the same frequency bands. Chapter 3 presents a single wire IF interface design for phased array receivers which enables simple IF backhaul for high data volume MIMO systems. Finally a outphasing power amplifier(PA) design is presented in chapter 4 along with a driver amplifier with digital amplitude modulation to achieve state of the art power back off efficiency, which reduces battery usage and thus increases mobility. The first part of this thesis demonstrates the use of orthogonal sequences along to N-path filters to achieve reconfigurable select/reject filtering of signals based on their spatial, spectral and code-domain properties. A frequency/code-domain reject and select filtering is proposed and implemented using N-path switching with passive inductors as correlators. Using inductors instead of capacitors in N-path filters is challenging because of large inductance value required for our application demands use of off-chip inductors, which comes with associated parasitics and lower self-resonance frequency. In this design a cascaded inductor approach and differential N-path filtering is used to overcome inductor parasitics and enable operation at 1 GHz. A code-domain notch filter followed by a code-domain select receiver is designed and implemented in 65-nm CMOS technology. Measurements demonstrate 0.5 GHz to 1.0 GHz filter tuning range, with a maximum 26dB rejection for a blocker signal with 8dBm power, while consuming 60mW (at 1GHz operation frequency) and occupying 1.2mm2 of die area. Second part of this thesis demonstrates a single wire IF interface to simplify scaling of millimeter-wave(mm-Wave) phased array systems while preserving the data from each element, this enables spatial multiplexing, virtual arrays for radar, digital beamforming(DBF), etc. However, per-element digitization results in a formidable I/O challenge in large-scale tiled MIMO mm-Wave arrays. This dissertation demonstrates a 28 GHz 4-element MIMO RX with a single-wire interface that multiplexes the baseband signals of all elements and the LO reference through code-domain multiplexing. System considerations are presented and the approach is validated through DBF after de-multiplexing of the baseband signals from the single wire. Each element in the array achieves 16 dB conversion gain and ∼ 7 dB noise figure(NF) while consuming 60 mA from 1.2 V. The IC occupies 5.75 mm² in 65-nm CMOS. Final part of this thesis describes the design and implementation of a digital outphasing PA at 28 GHz to achieve state of the art back of efficiency. Outphasing PA require branch PA units to act as voltage sources(very low output impedance), which is challenging at mm-Wave frequencies. In this PA design an approximate class-F operation is achieved by tuning PA load network for up to 3rd harmonic. A stacked PA architecture is used for individual PA units to achieve high maximum power output. Output-power further improved by utilizing a novel diode connected stack bias circuit to improve out-put swing. PA delivers a maximum output-power of 20 dBm with a peak power added efficiency(PAE) of 27% (PA along with driver stages) and 6 dB back-off PAE of 16.5%