Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Integrated Circuits and Systems for Millimeter-Wave Frequencies

In the first section of this thesis, mm-wave circuit- and system-level solutions for addition of multi-user service to conventional multi-antenna phased array architectures will be introduced. The proposed architecture will enhance the link capacity, co-channel user service and hardware cost compared to conventional solutions. Theory and design of the circuits and system are detailed and comprehensive measurement results are presented verifying the system-level functionality. First section is named A Millimeter-Wave Partially-Overlapped Beamforming-MIMO Receiver: Theory, Design, and Implementation. More specifically, this section presents an analysis and design of a partially-overlapped beamforming-MIMO architecture capable of achieving higher beamforming and spatial multiplexing gains with lower number of elements compared to conventional architectures. As a proof of concept, a 4-element beamforming-MIMO receiver (RX) covering 64-67 GHz frequency band enabling 2-stream concurrent reception is designed and measured. By partitioning the RX elements into two clusters and partially overlapping these clusters to create two 3-element beamformers, both phased-array (coherent beamforming) as well as MIMO (spatial multiplexing) features are simultaneously acquired. 6-bit phase shifters with 360° phase control and 5-bit VGAs with 11 dB range are designed to enable steering of the two RX clusters toward two arbitrary angular locations corresponding to two users. Fabricated in a 130-nm SiGe BiCMOS process, the RX achieves a 30.15 dB maximum direct conversion gain and a 9.8 dB minimum noise figure (NF) across 548 MHz IF bandwidth. S-parameter-based array factor measurements verify spatial filtering of the interference and spatial multiplexing in this RX chip.In the second section of this thesis, energy-efficient ultra-high speed transceiver architectures will be presented. Current high-speed transceivers rely on high-sampling-rate high-resolution power-hungry analog-to-digital converters or digital-to-analog converters at the interface of analog and digital circuitries. However, design of these backend data-converters are extremely power-hungry at very high speeds in a fully-integrated end-to-end scenario (i.e. RF-to-Bits, Bits-to-RF). Novel system-level architectures will be presented that obviate the need for such costly data converters and will significantly relax the complexity of digital signal-processing. The proposed architecture will result in orders of magnitude energy saving at ultra-high speeds. Theory, design, and measurement results of the highest-speed, highly energy-efficient fully-integrated end-to-end transceiver will be discussed in this section. Second section is named A Millimeter-Wave Energy-Efficient Direct-Demodulation Receiver: Theory, Design, and Implementation. More precisely, this section presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115-135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB was measured. A data-rate of 36 Gbps was wirelessly measured at 30 cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error-rate (BER) of 1e-6. The measured receiver sensitivity at this BER is -41.28 dBm. The prototype occupies 2.5 by 3.5 mm squared of die area including PADs and test circuits (2.5 mm squared active area) and consumes a total DC power of 200.25 mW

Design methods for 60GHz beamformers in CMOS

The 60GHz band is promising for applications such as high-speed short-range wireless personal-area network (WPAN), real-time video streaming at rates of several-Gbps, automotive radar, and mm-Wave imaging, since it provides a large amount of bandwidth that can freely (i.e. without a license) be used worldwide. However, transceivers at 60GHz pose several additional challenges over microwave transceivers. In addition to the circuit design challenges of implementing high performance 60GHz RF circuits in mainstream CMOS technology, the path loss at 60GHz is significantly higher than at microwave frequencies because of the smaller size of isotropic antennas. This can be overcome by using phased array technology. This thesis studies the new concepts and design techniques that can be used for 60GHz phased array systems. It starts with an overview of various applications at mm-wave frequencies, such as multi-Gbps radio at 60GHz, automotive radar and millimeter-wave imaging. System considerations of mm-wave receivers and transmitters are discussed, followed by the selection of a CMOS technology to implement millimeter-wave (60GHz) systems. The link budget of a 60GHz WPAN is analyzed, which leads to the introduction of phased array techniques to improve system performance. Different phased array architectures are studied and compared. The system requirements of phase shifters are discussed. Several types of conventional RF phase shifters are reviewed. A 60GHz 4-bit passive phase shifter is designed and implemented in a 65nm CMOS technology. Measurement results are presented and compared to published prior art. A 60GHz 4-bit active phase shifter is designed and integrated with low noise amplifier and combiner for a phased array receiver. This is implemented in a 65nm CMOS technology, and the measurement results are presented. The design of a 60GHz 4-bit active phase shifter and its integration with power amplifier is also presented for a phased array transmitter. This is implemented in a 65nm CMOS technology. The measurement results are also presented and compared to reported prior art. The integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package is investigated. Experimental results are presented and discussed

60 GHz transceiver circuits in SiGe-HBT and CMOS technologies

Die Erhöhung der Übertragungsrate von Kommunikationssystemen ist von hohem wissenschaftlichem und wirtschaftlichem Interesse. Die stetige Fortentwicklung dieser Systeme, sowohl unter Aspekten der Hard- als auch der Software, hat ein neues Technologiezeitalter eingeläutet. Verschiedene Szenarien, auf optischen, drahtgebundenen und drahtlosen Technologien basierend, wurden für diese Anwendungen entwickelt. Im 60 GHz ISM-Band (57 GHz bis 65 GHz) ist wegen der hohen Absorptionsverluste bei dieser Frequenz eine Kurzstrecken-Kommunikation mit hoher Datenrate von besonders hohem Interesse. Die Realisierung solcher Systeme erfolgt aufgrund von Kosten- und Massenproduktionsaspekten auf Basis von SiGe-HBT und CMOS Technologien. Schlüsselparameter eines 60 GHz-Transceivers sind eine hohe Ausgangsleistung, niedrige Rauschzahl, geringer Stromverbrauch und niedrige Herstellungskosten. Um den gesamten Frequenzbereich des 60 GHz ISM-Bandes abdecken zu können, wurden zahlreiche Transceivertopologien weltweit diskutiert. Die verfügbare Technologie mit ihren Schlüsselparametern ft, fmax stellt hierbei eine wichtige Randbedingung dar. In dieser Arbeit werden Aspekte des 60 GHz-Transceiver-Designs unter Verwendung einer 0,25 μm SiGe-HBT- und einer 90 nm CMOS-Technologie untersucht. Zunächst wird die Modellierung von passiven und aktiven Komponenten diskutiert. Verschiedene Techniken zur Modellextraktion basierend auf Messungen und elektromagnetischen Simulationen werden gezeigt. Für die wichtigsten passiven Bauelemente werden skalierbare Modelle entwickelt, um das Entwurfsverfahren zu präzisieren. Im nächsten Schritt werden 60 GHz CMOS- und SiGe-HBT- Leistungsverstärker untersucht. Basierend auf diesen Studien wurden zwei HBT und zwei CMOS-Endstufen konzipiert, realisiert und gemessen. Infolge der Verfügbarkeit einer hochgenauen Bauelemente-Bibliothek, ausgereifter Entwurfstechniken und der Verifikation auf Basis von EM-Simulationen konnte an den gemessenen Leistungsverstärkern eine hohe Ausgangsleistung mit guter Effizienz nachgewiesen werden. Die Ergebnisse zeigen weiterhin eine gute Übereinstimmung von Simulationen mit Messungen. Weiterhin wurden auf Basis einer 90 nm CMOS Technologie ein Heterodyne und ein OOK Transceiver entwickelt. Der Heterodyne-Transceiver mit einer Zwischenfrequenz von 20 GHz genügt dabei dem IEEE 802.15.3c Standard und erreicht eine Performance auf Höhe des internationalen Standes von Wissenschaft und Technik. Für den OOK Sender wurde eine neue Topologie entwickelt. Bei diesem Konzept bilden Modulator und Leistungsverstärker eine Einheit, woraus Vorteile hinsichtlich Ausgangsleistung, Effizienz und Chipgröße resultieren. Mit dieser Schaltung wurde in einem Systemtest eine Übertragungsrate von 6 Gbps über eine Entfernung von 4 m erfolgreich nachgewiesen.The rise of high-data-rate hungry applications has brought a new dawn to telecommunication technologies in both hardware and software development aspects. Different scenarios, mainly based on optical, coaxial and wireless systems, have been developed for these multi-gigabit communication systems. In these scenarios, the wireless system is utilized for indoor and short-range communication, which can ease the requirements on RF power and noise figure of the transceivers. However, the demand for multi-gigabit communication imposes a broadband performance requirement upon these wireless transceivers. This broadband performance requirement can be within the range of 2 GHz to 10 GHz. In order to cover such a broad frequency range, different transceiver circuit topologies have been suggested by many circuit designers. Due to the high oxygen loss in the 60 GHz range this 57 GHz to 65 GHz ISM band has attracted attention for high speed short-range communication. Moreover, the newly emerged low cost technologies (like, CMOS and SiGe HBT) have further attracted the industry to explore this communication band. The main requirements for a 60 GHz transceiver are high output power, low noise figure, low power consumption and broadband performance. To cover the whole 57 GHz to 65 GHz frequency band, numerous transceiver topologies are under discussion. The key parameter ft, fmax of the available technology define the achievable system performance. In this thesis, multiple aspects of the 60 GHz transceiver design based on the 90 nm CMOS and 0.25 μm SiGe HBT designs have been investigated. First, the modeling of passive and active components is presented. These components include capacitors, inductors, transformers, transmission lines, transistors, matching networks and RF pads. Different techniques for model extraction based on measurements and electromagnetic simulations have been examined. For inductors, transformers and capacitors scalable models have been developed. Further, the design techniques of 60 GHz CMOS and SiGe HBT power amplifiers have been studied. Based on these studies, two HBT and two CMOS power amplifiers have been designed, realized and measured. Due to accurate modeling and design techniques, high performance and good agreement with simulation has been achieved. Finally, two different types of transmitters (Heterodyne and OOK) based on the CMOS technology have been developed. The heterodyne transceiver, with an IF frequency of around 20 GHz, has been designed based on the IEEE 802.15.3c standard. This transmitter has achieved state of the art results with respect to output power, conversion gain and efficiency with a small chip size and low power consumption. For the OOK transmitter, a novel topology has been developed. In this topology, the modulator and the power amplifier have been integrated into one circuit. Due to many advantages of this new topology, this transmitter achieves higher output power and efficiency compared with state-of-the-art results. Furthermore, the realized circuit has been utilized within a wireless system where more than 6 Gbps has been successfully transmitted over a 4 m distance

Compact and Efficient Millimetre-Wave Circuits for Wideband Applications

Radio systems, along with the ever increasing processing power provided by computer technology, have altered many aspects of our society over the last century. Various gadgets and integrated electronics are found everywhere nowadays; many of these were science-fiction only a few decades ago. Most apparent is perhaps your ``smart phone'', possibly kept within arm's reach wherever you go, that provides various services, news updates, and social networking via wireless communications systems. The frameworks of the fifth generation wireless system is currently being developed worldwide. Inclusion of millimetre-wave technology promise high-speed piconets, wireless back-haul on pencil-beam links, and further functionality such as high-resolution radar imaging. This thesis addresses the challenge to provide signals at carrier frequencies in the millimetre-wave spectrum, and compact integrated transmitter front-ends of sub-wavelength dimensions. A radio frequency pulse generator, i.e. a ``wavelet genarator'', circuit is implemented using diodes and transistors in III--V compound semiconductor technology. This simple but energy-efficient front-end circuit can be controlled on the time-scale of picoseconds. Transmission of wireless data is thereby achieved at high symbol-rates and low power consumption per bit. A compact antenna is integrated with the transmitter circuit, without any intermediate transmission line. The result is a physically small, single-chip, transmitter front-end that can output high equivalent isotropically radiated power. This element radiation characteristic is wide-beam and suitable for array implementations

Applications of MATLAB in Science and Engineering

The book consists of 24 chapters illustrating a wide range of areas where MATLAB tools are applied. These areas include mathematics, physics, chemistry and chemical engineering, mechanical engineering, biological (molecular biology) and medical sciences, communication and control systems, digital signal, image and video processing, system modeling and simulation. Many interesting problems have been included throughout the book, and its contents will be beneficial for students and professionals in wide areas of interest