21 research outputs found

    적층 나노시트 구조의 음의 정전용량 전계 효과 트랜지스터

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    학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 최우영.The development of integrated circuit (IC) technology has continued to improve speed and capacity through miniaturization of devices. However, power density is increasing rapidly due to the increasing leakage current as miniaturization advances. Although the remarkable advancement of process technology has allowed complementary-metal-oxide-semiconductor (CMOS) technology to consistently overcome its constraints, the physical limitations of the metal-oxide-semiconductor field-effect transistor (MOSFET) are unmanageable. Accordingly, research on logic device is being divided into a CMOS-extension and a beyond-CMOS. CMOS-extension focuses on the gate-all-around field-effect transistors (GAAFETs) which is a promising architecture for future CMOS thanks to the excellent electrostatic gate controllability. Particularly, nanosheet (NS) architecture with high current drivability required in ICs, is the most promising. However, NS GAAFET has a trade-off relation between the controllability and the drivability, which requires the necessity of a higher-level effective oxide thickness (EOT) scaling for further scaling of NS GAAFET. On the other hand, beyond-CMOS mainly focuses on developing devices with novel mechanisms to overcome the MOSFETs' physical limits. Among several candidates, negative capacitance field-effect transistors (NCFETs) with exceptional CMOS compatibility and current drivability are highlighted as future logic devices for low-power, high-performance operation. Although the NCFET utilizing the negative capacitance (NC) effect of a ferroelectric has been demonstrated theoretically by the Landau model, it is challenging to be implemented due to the fact that stabilized NC and sub-thermionic subthreshold swing (SS) are incompatible. In this dissertation, a GAA NCFET that maintains a stable capacitance boosting by NC effect and exhibits high performance is demonstrated. A ferroelectric-antiferroelectric mixed-phase hafnium-zirconium-oxide (HZO) thin film was introduced, whose effect was confirmed by capacitors and FET experiments. Furthermore, the mixed-phase HZO was demonstrated on a stacked nanosheet gate-all-around (stacked NS GAA) structure, the advanced CMOS technology, which exhibits a superior gate controllability as well as a satisfactory drivability for ICs. The hysteresis-free stable NC operation with the superior performance was confirmed in NS GAA NCFET. The improved SS and on-current (Ion) compared to MOSFETs fabricated in the same manner were validated, and its feasibility as a low-power, high-performance logic device was proven based on a variety of figure of merits.집적회로 기술의 발전은 소자의 소형화를 통한 속도 및 용량의 향상을 위해 발전을 거듭해왔다. 그러나 소형화를 거듭할수록 증가하는 누설전류의 문제로 전력 밀도가 급격하게 증가하고 있다. 상보형 금속-산화막-반도체(CMOS) 기술은 눈부신 공정기술의 성장에 힘입어 한계를 끊임없이 극복해왔으나, 기존의 금속-산화막-반도체 전계-효과-트랜지스터(MOSFET)의 물리적 한계는 극복할 수 없는 문제이다. 이에 따라 논리 반도체에 관한 연구는 CMOS를 연장하는 방향과 CMOS를 뛰어넘는 방향으로 나뉘어 진행되고 있다. CMOS를 연장하는 방향은 뛰어난 정전기적 게이트 장악력을 갖는 차세대 CMOS 구조로 유망한 게이트-올-어라운드 전계-효과-트랜지스터(GAAFET)에 관한 연구가 주를 이룬다. 특히 높은 전류 구동력을 가질 수 있는 나노시트(NS) 구조가 가장 유망한데, 게이트 장악력이 전류 구동력과 상충된다는 단점이 있다. 이에 따라 NS GAAFET 기술을 위해서는 더 높은 수준의 유효산화막두께 (EOT) 스케일링이 필수적이다. 한편, CMOS를 뛰어넘는 방향의 연구는 MOSFET의 물리적 한계를 극복하기 위해 새로운 메커니즘을 갖는 소자를 개발하는 방향으로 이루어진다. 다양한 후보군 중 CMOS 호환성과 전류 구동능력이 뛰어난 음의 정전용량 전계-효과-트랜지스터(NCFET)이 저전력, 고성능 동작을 위한 미래 CMOS 소자로 각광받고 있다. 강유전체의 음의 정전용량 (NC) 효과를 이용한 NCFET은 Landau 모델에 의해 이론적으로 증명되었으나, 열역학적으로 안정한 상태와 60 mV/dec 이하의 문턱전압-이하-기울기(SS)를 동시에 구현하기 불가능하다는 문제가 있다. 본 학위논문에서는 안정한 정전용량 향상 특성을 가지며 높은 성능을 갖는 NS GAA NCFET을 구현하였다. 강유전체(ferroelectric)-반강유전체(antiferroelectric) 혼합상(mixed-phase) 하프늄-지르코늄-옥사이드(HZO) 박막의 정전용량 향상 효과를 커패시터 및 FET 제작을 통해 효과를 검증하였다. 또한 높은 게이트 장악력을 가지며 집적회로에서 요구하는 전류 구동력을 만족시킬 수 있는 적층형 나노시트 게이트-올-어라운드(stacked NS GAA) 구조에 혼합상 NC 박막을 적용한 FET을 시연하고 성능의 우수성을 확인하였다. 동일하게 제작된 MOSFET 대비 향상된 SS와 구동 전류(Ion)를 확인하였고, 다양한 성능 지수를 토대로 저전력, 고성능 로직 소자로서의 타당성을 검증하였다.Abstract i Contents iv List of Table vii List of Figures viii Chapter 1 Introduction 1 1.1 Power and Area Scaling Challenges 1 1.2 Nanosheet Gate-All-Around FETs 5 1.2.1 Gate-All-Around FETs 5 1.2.2 Nanosheet GAAFETs 6 1.3 Negative Capacitance FETs 11 1.3.1 Negative Capacitance in Ferroelectric Materials 11 1.3.2 Negative Capacitance for Steep Switching Devices 14 1.3.3 Stable NC vs. Sub-thermionic SS 17 1.4 Scope and Organization of Dissertation 21 Chapter 2 Stacked NS GAA NCFET with Ferroelectric-Antiferroelectric-Mixed-Phase HZO 22 2.1 Mixed-Phase HZO for Capacitance Boosting 22 2.2 NS GAA NCFET using Mixed-Phase HZO 25 Chapter 3 HZO ALD Stack Optimization 28 3.1 Metal-Ferroelectric-Interlayer-Silicon (MFIS) / MFM Capacitors 29 3.1.1 Fabrication of MFIS Capacitors 29 3.1.2 Electrical Characteristics of MFIS / MFM Capacitors 33 3.2 SOI Planar NCFETs 38 3.2.1 DC Measurements 38 3.2.2 Direct Capacitance Measurements 47 3.2.3 Speed Measurements 49 Chapter 4 Device Fabrication of Stacked NS GAA NCFET 51 4.1 Initial Process Flow of NS GAA NCFET 52 4.2 Process Issues and Solution 56 4.2.1 External Resistance 56 4.2.2 TiN Gate Sidewall Spacer 60 4.2.3 Unintentionally Etched Sacrificial Layer 65 4.2.4 Discussions 68 4.3 Channel Release Process 69 4.3.1 Consideration in Channel Release Process 69 4.3.2 Methods for SiGe Selective Etching 72 4.3.3 SiGe Selective Etching using Carboxylic Acid Solution 75 4.4 Revised Process of NS GAA NCFET 78 Chapter 5 Electrical Characteristics of Fabricated NS GAA NCFET 84 5.1 DC Characteristics 85 5.1.1 NS GAA NCFET vs. Planar SOI NCFET 85 5.1.2 Performance Enhancement of NS GAA NCFET 88 5.1.3 Performance Evaluation 96 5.2 Operating Temperature Properties 99 Chapter 6 Conclusion 102 Bibliography 105 초 록 115박

    Understanding Quantum Technologies 2022

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    Understanding Quantum Technologies 2022 is a creative-commons ebook that provides a unique 360 degrees overview of quantum technologies from science and technology to geopolitical and societal issues. It covers quantum physics history, quantum physics 101, gate-based quantum computing, quantum computing engineering (including quantum error corrections and quantum computing energetics), quantum computing hardware (all qubit types, including quantum annealing and quantum simulation paradigms, history, science, research, implementation and vendors), quantum enabling technologies (cryogenics, control electronics, photonics, components fabs, raw materials), quantum computing algorithms, software development tools and use cases, unconventional computing (potential alternatives to quantum and classical computing), quantum telecommunications and cryptography, quantum sensing, quantum technologies around the world, quantum technologies societal impact and even quantum fake sciences. The main audience are computer science engineers, developers and IT specialists as well as quantum scientists and students who want to acquire a global view of how quantum technologies work, and particularly quantum computing. This version is an extensive update to the 2021 edition published in October 2021.Comment: 1132 pages, 920 figures, Letter forma

    Miniaturized Transistors, Volume II

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    In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

    Microscopy Conference 2021 (MC 2021) - Proceedings

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    Das Dokument enthält die Kurzfassungen der Beiträge aller Teilnehmer an der Mikroskopiekonferenz "MC 2021"

    Cutting Edge Nanotechnology

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    The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

    Design and implementation of lightweight encryption algorithm using prince cipher

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    Lightweight cryptography is widely deployed on low-resource devices that has limited computing power, low memory size and power resource. With the rising of pervasive computing, more devices are connected online, and new requirement on encryption model that emphasizes on ultra-fast response time is introduced. Most of the available lightweight cryptographies are round-based designs, they are able to achieve high throughput via pipelining the round functions, however the response time is not ideal. The Prince cipher is the first lightweight block cipher developed to speed up the latency of the algorithm. Compare to other block ciphers, the Prince is able to yield low latency with very competitive area utilization, hence it is a promising choice for low-resource devices that emphasize of response time. In this work, the Prince cipher will be designed and synthesize in different implementation including roundper- cycle, single-cycle and reduced multicycle implementations. The synthesis results had suggested that the single-cycle Prince cipher is achievable with almost 40% reduction in encryption latency. This indicates the possibility of instantaneous encryption as the full operation can be performed within a single clock cycle and no warm-up phase is needed. However, the implementation using loop unrolling also introduced larger gate count and therefore the design will have bigger silicon footprint. With the improvement of chip technology, it is possible to absorb the increment in of the gate count in the Prince cipher in exchange for performance. Furthermore, the modern SOC design often involves many-core designs that have high-bandwidth, packet-switched network design. These applications need the data to be processed as fast as possible, hence the conventional high throughput looping approaches are not desirable as they might limit the bandwidth of these high-speed buses within the SOC

    Numerical Simulations

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    This book will interest researchers, scientists, engineers and graduate students in many disciplines, who make use of mathematical modeling and computer simulation. Although it represents only a small sample of the research activity on numerical simulations, the book will certainly serve as a valuable tool for researchers interested in getting involved in this multidisciplinary field. It will be useful to encourage further experimental and theoretical researches in the above mentioned areas of numerical simulation

    Cellulose Nanocrystal Chiral Structures for Electronics and Photonics

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    This dissertation reports on the integration of cellulose nanocrystals (CNCs) as photonic films into optoelectronic devices, where the films’ inherent left-handed mesoporous chiral nematic structure acts as a circular polarized light (CPL) filter in the visible light range. The outcome demonstrates for the first time micro- scopic semiconducting devices based on cellulose, capable of producing specific electronic outputs when irradiated with either left- or right- handed CPL (LCPL and RCPL, respectively). For this proof-of-concept two distinct optoelectronic devices are targeted: a thin-film field-effect transistor and a thin-film photodiode, spanning the whole visible electromagnetic spectrum. The devices are jointly developed each one with a specific type of CNC, presenting photonic bandgaps that are tuned for the active layer of the devices. On the one hand, lab-produced (home-made CNCs – HM-CNCs) are synthesized through sulfuric acid hydrol- ysis, yielding HM-CNC films with a photonic bandgap in the blue/UV region. On the other hand, industrially produced Na neutralized spray-dried CNCs by CelluForce (C-CNCs) are studied on behalf of their redispersion in water to yield C-CNC films with a photonic bandgap in the green/red region. The work is essentially divided into three main parts: • Study of liquid crystalline and photonic properties of HM-CNCs and C- CNCs in aqueous suspensions (Chapter 3) • Implementation of HM-CNCs into field-effect transistors (Chapter 5) • Implementation of C-CNCs into thin-film photodiodes (Chapter 6) The main objective of Chapter 5 deals with the implementation of HM-CNCs films, optimized through the first Objective in Chapter 3, into field-effect tran- sistors based on amorphous indium-gallium-zinc-oxide (a-IGZO) as the semicon- ductor. In the resulting devices the HM-CNC films take simultaneously the role of the devices’ dielectric as a solid-state electrolyte and as a photonic filter for CPL. Consequently, this study encompasses two sub-objectives, connected firstly to the study of the electrochemical properties of these films and their success- ful integration into field-effect transistors without compromising self-assembly behavior. And secondly, successful proof of CPL sensing capabilities of these devices. The final study shows the incorporation of C-CNC films, into amorphous silicon-based thin-film photodiodes, achieving a light sensor capable of discrimi- nating between RCPL and LCPL. The spectral response of the fabricated photo- diodes is maximum for specific wavelengths in the green/red region. Irradiating the devices in these wavelengths they produce photocurrents that are over 50% distinct between RCPL and LCPL. Fast transient responses (on the order of ms) of CPL are shown with possible logic operations, as well as humidity sensing. Films produced through the methods described in Chapter 3 show promis- ing properties for their application in sensing, co-templating, enantioselectivity, photonic pigments or anti-counterfeiting. The insights presented in Section 5.1 contribute to applications in solid-state ionics of mesoporous structures or the combination of optically active electrolytes capable of providing unique func- tionalities in ion-gated transistors and circuitry. Finally, the types of devices pro- duced in Section 5.2 and Chapter 6 may find applications in photonics, emission, conversion, or sensing with CPL but also imaging, spintronics, optoelectronic counterfeiting or information processing with logic states that depend solely on the handedness of the incident light.Esta dissertação é dedicada ao estudo de nanocristais de celulose (cellulose nanocrystals - CNCs) e à sua integração como filmes fotónicos em dispositivos optoelectrónicos, explorando a sua estrutura nemática quiral com orientação de rotação para esquerda como um filtro de luz polarizada circularmente (circu- lar polarized light - CPL) no comprimento de onda visível. Os resultados deste trabalho demonstram dispositivos microscópicos à base de celulose, capazes de responder com sinais elétricos específicos quando irradiados por CPL à esquerda (LCPL) ou CPL à direita (RCPL). Para esta prova-de-conceito são destacados dois dispositivos optoelectrónicos distintos: transístores e fotodíodos. Os dispositivos desenvolvidos incorporam diferentes tipos de CNCs com um hiato fotónico espe- cífico correspondente à região de absorção das camadas ativas dos dispositivos. De um lado são sintetizados CNCs em laboratório (home-made CNCs – HM-CNCs) que resultarão filmes fotónicos com um hiato no Azul/UV. De outro lado, CNCs comerciais da CelluForce (C-CNCs), em forma de pó. A redispersão desse tipo de CNCs em água é investigada, e resulta em filmes fotónicos com um hiato na região do verde/vermelho. Essencialmente, o trabalho está divido em três partes principais: • Estudo das propriedades líquidas cristalinas e fotónicas de suspensões aquo- sas de HM-CNCs e C-CNCs (Capítulo 3) • Implementação de HM-CNCs em transístores (Capítulo 5) • Implementação de C-CNCs em fotodíodos (Capítulo 6) Capítulo 5 estuda a implementação de filmes de HM-CNCs, otimizados no objetivo do Capítulo 3, em transístores de efeito de campo onde o semicondutor é o óxido de índio-gálio-zinco amorfo (a-IGZO). Nos dispositivos finais, o filme de HM-CNCs assume uma dupla funcionalidade: funciona como o dielétrico do transístor (na forma de um eletrólito de estado sólido), e atua como um filtro seletivo de CPL. Logo, esta parte está divida em dois sub-objetivos: a primeira estuda as propriedades eletroquímicas dos filmes de HM-CNCs, e a sua integração em transístores de efeito de campo sem perda das propriedades de self-assembly, enquanto a segunda parte é dedicada à prova de conceito da deteção seletiva de CPL. O estudo final demonstra a incorporação de filmes de C-CNCs em fotodíodos baseados em silício amorfo, que resulta em sensores de luz capazes de diferenciar entre os dois estados de CPL. A resposta espetral dos fotodíodos é máxima para comprimentos de onda específicos na região do verde e do vermelho. Ao irradiar os dispositivos finais nesses comprimentos de onda com CPL, estes apresentam uma diferença de 50% nas foto-correntes medidas para cada um dos dois estados de CPL. Os dispositivos finais mostram tempos de resposta rápidos (na ordem dos ms), o que os habilita a serem implementados em circuitos para operações lógicas baseadas em estados de polarização e também como sensores de humidade. Filmes produzidos no Capítulo 3, mostram propriedades promissoras para a sua aplicação em sensores, pigmentos fotónicos, e na área de anti-falsificação e segurança. Os resultados da Secção 5.1 contribuem para aplicações em iónica de estado sólido de estruturas mesoporosas, ou a combinação de eletrólitos ótica- mente ativos. Por fim, os dispositivos fabricados na Secção 5.2 e Capítulo 6, podem ser aplicados em áreas de fotónica, emissão, conversão ou sensores de CPL, mas também imagiologia, spintrónica, anti-falsificação por dispositivos optoelectró- nicos, ou processamento de informação com estados lógicos que dependem da polarização da radiação incidente

    GeSn semiconductor for micro-nanoelectronic applications

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    Within the last few years the steady electronic evolution lead the semiconductor world to study innovative device architectures and new materials able to replace Si platforms. In this scenario Ge1-xSnx alloy attracts the interest of the scientific community due to its ability to tune the material bandgap as a function of Sn content and its extreme compatibility with Si processing. Although the enhanced optical properties of Ge1-xSnx are evident, the augmented electrical properties such as the higher electron and holes mobility are also beneficial for metal oxide semiconductor. Therefore the alloy is expected to be a potential solution to integrate both electrical and optical devices. On one hand, several theoretical and experimental works depict the Ge1-xSnx alloy as a novel and fascinating solution to replace Si; on the other hand the material novelty forces us to enhance the knowledge of its fundamental physical and chemical properties, re-adapting the processing steps necessary to develop electronic and optical devices. In this dissertation a comprehensive study on Ge1-xSnx has been undertaken and discussed analysing a wide range of topics. The first chapter provides a detailed theoretical study on the electronic properties of the GeSn performed using first principle methods; subsequently the data obtained have been inserted into a TCAD software in order to create and calibrate a library used to simulate electrical devices. It is important to note, that at the beginning of this PhD GeSn was not an available material in the Synopsys device software, and thus it had to be defined from scratch As a next point, since the ever decreasing device size push toward the definition of Ohmic contacts, different stanogermanide films have been thoroughly analysed using various metals (Ni, Pt and Ti) annealed with two distinct methodologies (Rapid Thermal Annealing and Laser Thermal Annealing). Subsequently, considering the material limitation such as the limited thermal budget and the Sn segregation, an exhaustive study on the material doping has been firstly discussed theoretically and after experimentally characterized using both classical ion implantation and layer deposition techniques. The different building blocks of Field Effect Transistors have been investigated and tuned individually with the aim to develop FET devices with bottom up approach. Then, Field Effect Transistor devices using GeSn NWs grown by a VLS methodology with Sn composition ranging from (0.03-0.09 at.%) have been developed and extensively characterized with the state of the art present in literature. Finally the analysis of highly selective etch recipes lead to the development of sub-nm device configuration such as Gate-All-Around (GAA) structure obtained using classical top down lithography approach. The innovative structure was electrically characterized highlighting the possibility to obtain decananometer device architecture with this innovative alloy. Lastly thesis summary and final outlooks were reported with the aim to outline the thesis contribution and the future material investigations

    Impacto da variabilidade PVT em somadores construídos com XORs

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    A operação de soma é a mais usada em Unidades Lógicas e Aritméticas (ULA). A ULA é a unidade mais importante no processamento de dados. Em sistemas digitais, é desejado um somador completo com baixo consumo de energia e um alto desempenho. O somador completo faz parte do caminho crítico em sistemas computacionais, ele pode ser implementado de diversas maneiras, a maioria delas tendo como seu principal sub-circuito a porta lógica OU-exclusivo (XOR). Consequentemente, o estudo de somadores completos compostos por combinações de portas lógicas XOR é de grande valia para pesquisas na literatura. Melhorias nos módulos aritméticos pode reduzir significativamente o consumo de potência dos sistemas, mas em tecnologias nanométricas é necessário considerar o impacto da variabilidade. Esse trabalho tem como objetivo analisar projetos de somadores completos que quando submetidos aos efeitos de variabilidade devem ser robustos, ter um bom desempenho e mostrar bons resultados em consumo de energia, quando estão operando em tensão nominal e em tensão de quase limiar. Além disso, foi utilizada uma técnica chamada de célula de desacoplamento (Dcell) visando uma alternativa para a redução da variabilidade de processo. Esse trabalho analisa e compara 4 somadores tradicionais e 9 somadores completos construídos através de 3 blocos lógicos, dos quais 2 deles são substituídos por portas lógicas XOR, em uma tecnologia FinFET de 7nm. Foi observado que circuitos somadores que foram construídos usando a XOR da família lógica CMOS, especialmente no segundo bloco, obtiveram piores resultados de desempenho e consumo energético. Somadores operando em tensão nominal são cerca de 80% mais robustos quanto ao impacto da variabilidade de processo no consumo máximo. A operação em quase limiar implica em uma alta sensibilidade no desempenho e consumo, alcançando mais de 300% nos piores casos. Em relação à variabilidade de processo, foi verificado um aumento de sensibilidade de cerca de 40% no desempenho quando foram utilizadas a XOR V5 e a XOR V8 no segundo bloco dos somadores quando operando em tensão nominal. Para a operação em tensão de quase limiar o uso da metodologia proposta nesse trabalho mostrou ser uma boa opção para alcançar uma maior robustez quanto ao consumo dos circuitos. Considerando o uso da Dcell, na operação em tensão nominal, foi verificado uma redução no desempenho juntamente com uma redução na variabilidade. O melhor caso foi o somador FAV5V8 que para um aumento de 20% no atraso, obteve uma redução de 20% na variabilidade. Em relação ao consumo, houve uma redução de 16% na potência dinâmica, juntamente com uma redução de quase 30% na variabilidade, como o que ocorreu com o somador FAV8V1. Foi possível observar casos de redução da variabilidade em mais de 40% com um pequeno aumento no consumo dinâmico. O uso dessa técnica teve um alto impacto nos resultados de circuitos que operavam em tensão de quase limiar, chegando em alguns casos a mais de 40% de redução do desempenho para uma pequena redução na variabilidade. Quanto ao consumo, nesse caso, os somadores tradicionais foram os menos afetados, e novamente o uso da XOR V8 no segundo bloco para construção dos somadores mostrou ser uma boa opção para aumento da robustez dos circuitos.The sum operation is the most used in the Arithmetic and Logic Units (ALU). In digital systems, a complete adder with low energy consumption and high performance is desired. The full adder is part of the critical path in computer systems. It can be implemented in several ways, most of them having the OR-exclusive logic gate (XOR) as its main sub-circuit. Consequently, the study of full adders composed of combinations of XOR logic gates has a great value in the literature. Improvements in arithmetic modules can significantly reduce the power consumption of systems, however, in nanometric technologies it is necessary to consider the impact of variability. This work aims to analyse designs of full adders considering variability effects, comparing performance and energy consumption when operating at nominal voltage and also at near threshold voltage. In addition, a technique called decoupling cell (Dcell) was used to provide an alternative for reducing process variability. This work analyses and compares four traditional adders and nine adders built using three logic blocks, where two of them are replaced by XOR logic gates, in a 7nm FinFET technology. It was observed that full adders that were built using the XOR of the CMOS logic family, especially in the second block, had worse results in performance and energy consumption. Full adders operating at nominal voltage regime are about 80% more robust in terms of the impact of process variability on maximum consumption. The near threshold operation implies a high sensitivity in performance and consumption, reaching more than 300% in the worst cases. Regarding the process variability, there was an increase in sensitivity of about 40% in performance when the XOR V5 and XOR V8 were used in the second block of the adder when operating at nominal voltage. For the voltage operation of near threshold, the use of the methodology proposed in this work demonstrate to be a good option to achieve greater robustness regarding the consumption of the circuits. Considering the use of Dcell, in the operation at nominal voltage, a reduction in performance was verified together with a reduction in variability. The best case was the adder FAV5V8 which for a 20% increase in delay, obtained a reduction of 20% in variability. In relation to dynamic consumption, there was a 16% reduction in power, together with a reduction of almost 30% in variability, as occurred with the FAV8V1 adder. It was possible to observe cases of reduced variability by more than 40% with a small increase in dynamic consumption. The use of this technique had a high impact on the results of circuits operating at near threshold voltage, in some cases reaching more than 40% reduction in performance for a small reduction in variability. For consumption, in this case, the traditional full adders were the least affected, and again the use of the XOR V8 in the second block for the construction of the adder proved to be a good option for increasing the robustness of the circuits
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