6,983 research outputs found

    A Readout System for the STAR Time Projection Chamber

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    We describe the readout electronics for the STAR Time Projection Chamber. The system is made up of 136,608 channels of waveform digitizer, each sampling 512 time samples at 6-12 Mega-samples per second. The noise level is about 1000 electrons, and the dynamic range is 800:1, allowing for good energy loss (dE/dxdE/dx) measurement for particles with energy losses up to 40 times minimum ionizing. The system is functioning well, with more than 99% of the channels working within specifications.Comment: 22 pages + 8 separate figures; 2 figures are .jpg photos to appear in Nuclear Instruments and Method

    Bridging the Testing Speed Gap: Design for Delay Testability

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    The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addresse

    PIM source identification using vibration modulation method

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    “In Section 1, passive intermodulation (PIM) is introduced and the mechanism of it is briefly explained. Then, the up-to-date PIM testing and source identification method in the industrial and academia worlds will be summarized. The vibration modulation method for PIM source identification is proposed in Section 2. Different vibration sources were tested and compared, and the test results showed that the vibration modulation method is able to identify PIM source with good accuracy. Section 3 outlines a special PIM source identification system built based on the vibration modulation system. The two subsystems, PIM receiver and PIM vibrator, are illustrated in detail. In Section 4, PIM source identification tests were conducted on a base station antenna using the PIM source identification system. The experiment results show the system was able to pinpoint the PIM source accurately”--Abstract, page iii

    Time-division multiplexing for testing SoCs with DVS and multiple voltage islands

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    LTE Spectrum Sharing Research Testbed: Integrated Hardware, Software, Network and Data

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    This paper presents Virginia Tech's wireless testbed supporting research on long-term evolution (LTE) signaling and radio frequency (RF) spectrum coexistence. LTE is continuously refined and new features released. As the communications contexts for LTE expand, new research problems arise and include operation in harsh RF signaling environments and coexistence with other radios. Our testbed provides an integrated research tool for investigating these and other research problems; it allows analyzing the severity of the problem, designing and rapidly prototyping solutions, and assessing them with standard-compliant equipment and test procedures. The modular testbed integrates general-purpose software-defined radio hardware, LTE-specific test equipment, RF components, free open-source and commercial LTE software, a configurable RF network and recorded radar waveform samples. It supports RF channel emulated and over-the-air radiated modes. The testbed can be remotely accessed and configured. An RF switching network allows for designing many different experiments that can involve a variety of real and virtual radios with support for multiple-input multiple-output (MIMO) antenna operation. We present the testbed, the research it has enabled and some valuable lessons that we learned and that may help designing, developing, and operating future wireless testbeds.Comment: In Proceeding of the 10th ACM International Workshop on Wireless Network Testbeds, Experimental Evaluation & Characterization (WiNTECH), Snowbird, Utah, October 201

    A 128K-bit CCD buffer memory system

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    A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications
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