KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

High-Efficiency Millimeter-Wave Front-Ends for Large Phased-Array Transmitters

The ever-increasing demand for wireless broadband connectivity requires infrastructure capable of supporting data transfer rates at multi-Gbps. To accommodate such heavy traffic, the channel capacity for the given spectrum must be utilized as efficiently as possible. Wideband millimeter-wave phased-array systems can enhance the capacity of the channel by providing multiple steerable directional beams. However the cost, complexity, and high power consumption of phased-array systems are key barriers to the commercialization of such technology. Silicon-based beam-former chips and scalable phased-array technology offer promising solutions to lower the cost of phased-array systems. However, the implementation of low-power phased-array architectures is still a challenge. Millimeter-wave power generation in silicon beam-formers suffers from low efficiency. The stringent linearity requirements for multi-beam wideband arrays further limits the achievable efficiency. In scalable phased-arrays, each module consists of an antenna sub-array and a beam-former chip that feeds the antenna elements. To improve efficiency, a design methodology that considers the beam-former chip and the antenna array as one entity is necessary. In this thesis, power-efficient solutions for a millimeter-wave phased-array transmitter are studied and different high-efficiency power amplifier structures for broadband applications are proposed. Initially, the design of a novel 27-30 GHz RF front-end consisting of a variable gain amplifier, a 360 degree phase shifter, and a two-stage linear power amplifier with output power of 12 dBm is described. It is fabricated using 0.13 $\mu m$ SiGe technology. This chip serves as the RF core of a beam-former chip with eight outputs for feeding a 2$\times$2 dual-feed sub-array. Such sub-arrays are used as part of large phased-arrays for SATCOM infrastructure. Measurement results show 26.7 \% total efficiency for the designed chip. The chip achieves the highest efficiency among Ka-band phased-array transmitters reported in the literature. In addition, original transformer-based output matching structures are proposed for harmonic-tuned power amplifiers. Harmonic-tuned power amplifiers have high peak-efficiency but their complicated output matching structure can limit their use in beam-former RF front-ends. The proposed output matching structures have the layout footprint of a transformer, making their use in beam-former chips feasible. A 26-38 GHz power amplifier based on a non-inverting 1:1 transformer is fabricated. A measured efficiency of more than 27 \% is achieved across the band with an output power of 12 dBm. Furthermore, two continuous class $F^{-1}$ power amplifiers using 1:1 inverting transformers are described. Simulation results show a peak-efficiency of 35 \% and output power of 12 dBm from 24 to 30 GHz. A common-base power amplifier with inverting transformer output matching is also demonstrated. This amplifier achieves a peak-efficiency of 42 \% and peak output power of 16 dBm. Finally, a low-loss Ka-band re-configurable output matching structure based on tunable lines is proposed and implemented. A double-stub matching structure with three tunable segments is proposed to maximize the impedance matching coverage. This structure can potentially compensate for the antenna impedance variation in phased-array antennas

Apport des lignes à ondes lentes S-CPW aux performances d'un front-end millimétrique en technologie CMOS avancée

L objectif de ce travail est de concevoir et de caractériser un front-end millimétriqueutilisant des lignes de propagation à ondes lentes S-CPW optimisées en technologies CMOS avancées.Ces lignes présentant des facteurs de qualité 2 à 3 fois supérieurs à ceux des lignes classiques de typemicroruban ou CPW.Dans le premier chapitre, l impact de l évolution des noeuds technologiques CMOS sur lesperformances des transistors MOS aux fréquences millimétriques et sur les lignes de propagation ainsiqu un état de l art concernant les performances des front-end sont présentés. Le deuxième chapitreconcerne la réalisation des lignes S-CPW dans différentes technologies CMOS et la validation d unmodèle phénoménologique électrique équivalent. Le troisième chapitre est dédié à la conceptiond amplificateurs de puissance à 60 GHz utilisant ces lignes S-CPW en technologies CMOS 45 et65 nm. Cette étude a permis de mettre en évidence l apport des lignes à ondes lentes aux performancesdes amplificateurs de puissance fonctionnant dans la gamme des fréquences millimétriques. Uneméthode de conception basée sur les règles d électro-migration et permettant une optimisation desperformances a été développée. Finalement, un amplificateur faible bruit et un commutateur d antennetravaillant à 60 GHz et à base de lignes S-CPW ont été conçus en technologie CMOS 65 nm afin degénéraliser l impact de ce type de lignes sur les performances des front-end millimétriques.The objective of this work is to design and characterize a millimeter-wave front-end usingthe optimized slow-wave transmission lines S-CPW in advanced CMOS technologies. The qualityfactor of these transmission lines is twice to three times higher than that of the conventionaltransmission lines such as microstrip lines and coplanar waveguides.In the first chapter, the influence of CMOS scaling-down on the performance of transistors atmillimeter-wave frequencies and on the transmission lines was studied. In addition, a state of the artwith regard to the performance of the front-end was presented. The second chapter concerns about therealization of the S-CPW lines in different CMOS technologies and the validation of an electricalequivalent model. The third chapter is dedicated to the design of 60-GHz power amplifiers using theseS-CPW lines in CMOS 45 and 65 nm technologies. This study highlighted the performanceenhancement of power amplifiers operating at millimeter-wave frequencies by using the slow-wavetransmission lines. A design method based on the electro-migration rules was also developed. Finally,a low noise amplifier and an antenna switch operating at 60 GHz were designed in CMOS 65 nm inorder to generalize the impact of such transmission lines on the performance of the millimeter-wavefront-end.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Push-Pull Based High Efficiency and High Power Broadband Power Amplifiers for Wireless Base Stations

The monthly data throughput by 2021 is forecasted to be ten times that of December 2015. As a result of the on going dramatic increase in demand, service providers are assigned new frequency bands to accommodate more channels to carry more data. However, the usable part of the spectrum is a limited resource so modern communication signals were designed to be more spectrally efficient to send more bits over the same channel bandwidth. However, these spectrally efficient signals have high PAPR. The immediate reaction to these changes was to add additional RF front-end branches to accommodate the new frequency bands. Initially, the PAs used at the time were not optimized for back-off efficiency and where operating at low efficiency which caused significant increase in heat generation for the same average power produced which in turn increased cooling costs and reduced the life time of the PA. After the introduction of back-off efficiency enhancement techniques the PAs became more efficient however they were limited in bandwidth which is typically 10-15%. This work focuses on reducing the redundancy of power amplifiers in communication base stations while maintaining high back-off efficiency. After exploring the literature to understand the limitations of current implementations, it was found that the push-pull topology is often used at low frequency in broadband high power PAs. In the absence of a complimentary transistor pairs the push-pull implantation requires the use of balanced to unbalanced (balun) transformers. Various balun implantations were hence investigated to identify the most suitable option for broadband planar implementation. As a result, a methodology was proposed to co-design the balun and the matching network in order to have better control over the harmonic impedance. An 85 W push-pull PA was then designed based on the proposed methodology with a multi-octave bandwidth as a demonstration of the broadband potential of push-pull PAs at RF frequencies. Next, the two most popular techniques for back-off efficiency enhancement, i.e., ET and load modulation, were studied and the principle of load modulation was found to be more suitable for broadband signal transmission. The Doherty architecture is the most common implementation of load modulation and it comes in two basic variations, the PCL and SCL DPAs. The original architecture concepts are not only band limited but also ill-suited for high frequency designs where the transistors' parasitics introduce significant effect. However, later literature expanded on the original concept of the PCL variation which provided the needed flexibility for wider bandwidth implementations at a higher frequency. Using the broadband implementation and the co-design methodology two push-pull amplifiers were used in a PCL DPA topology and demonstrated that the push-pull utilization doesn't have a significant impact on the bandwidth of the output combiner as an octave bandwidth was achieved with the use of digital Doherty. Lastly, the thesis proposes a new approach for designing high power DPAs with extended bandwidth. It starts with a generic SCL DPA architecture to derive the equations that relate its underlying combiner's ABCD parameters to the transistor's optimum impedance and load impedance. These equations featured the possibility of significantly increasing the load impedance in SCL DPA compared to the one of the popular PCL DPA architecture. This is particularly beneficial when targeting very high power DPAs for macro-cell base stations and broadcast applications where very low load impedance can seriously complicate the design and limit the achievable bandwidth. To further maximize the load impedance increase, the proposed SCL DPA uses a push-pull topology for the main and peaking amplifier stages. A low-loss planar balanced to unbalanced transformer (balun) combiner network is then utilized to realize the SCL DPA combining. The proposed approach was finally applied to design a proof-of-concept 350 W SCL DPA which operates over the band spanning from 720 to 980 MHz. The prototype demonstrated a peak output power of about 55 dBm over a 30% FBW with a 6 dB back-off efficiency, measured using pulsed signal, between 46.6% and 54.6%. Furthermore, the modulated signal based measurement results confirmed the linearizability of the SCL DPA prototype while maintaining a back-off efficiency over 50% for a 7.1 dB peak to average power ratio signal