Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

In Situ Automatic Analog Circuit Calibration and Optimization

As semiconductor technology scales down, the variations of active/passive device characteristics after fabrication are getting more and more significant. As a result, many circuits need more accuracy margin to meet minimum accuracy specifications over huge process-voltage-temperature (PVT) variations. Although, overdesigning a circuit is sometimes not a feasible option because of excessive accuracy margin that requires high power consumption and large area. Consequently, calibration/tuning circuits that can automatically detect and compensate the variations have been researched for analog circuits to make better trade-offs among accuracy, power consumption, and area. The first part of this dissertation shows that a newly proposed in situ calibration circuit for a current reference can relax the sharp trade-off between the temperature coefficient accuracy and the power consumption of the current reference. Prototype chips fabricated in a 180 nm CMOS technology generate 1 nA and achieve an average temperature coefficient of 289 ppm/°C and an average line sensitivity of 1.4 %/V with no help from a multiple-temperature trimming. Compared with other state-of-the-art current references that do not need a multiple-temperature trimming, the proposed circuit consumes at least 74% less power, while maintaining similar or higher accuracy. The second part of this dissertation proves that a newly proposed multidimensional in situ analog circuit optimization platform can optimize a Tow-Thomas bandpass biquad. Unlike conventional calibration/tuning approaches, which only handle one or two frequency-domain characteristics, the proposed platform optimizes the power consumption, frequency-, and time-domain characteristics of the biquad to make a better trade-off between the accuracy and the power consumption of the biquad. Simulation results show that this platform reduces the gain-bandwidth product of op-amps in the biquad by 80% while reducing the standard deviations of frequency- and time-domain characteristics by 82%. Measurement results of a prototype chip fabricated in a 180 nm CMOS technology also show that this platform can save maximum 71% of the power consumption of the biquad while the biquad maintains its frequency-domain characteristics: Q, ωO and the gain at ωO